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CS4804 Datenblatt(PDF) 1 Page - Applied Micro Circuits Corporation |
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CS4804 Datenblatt(HTML) 1 Page - Applied Micro Circuits Corporation |
1 / 2 page Features S4804CBI Block Diagram RHINE OC-48 / 4xOC-12 / 16xOC-3 SONET/SDH FRAMER AND POS/ATM MAPPER Part Number - S4804CBI41 Product Brief Version 2.0 - January 2002 PRODUCT BRIEF AMCC Production Release Information - The information con- tained in this document is about a product in its fully tested and characterized phase. All features described herein are supported. Contact AMCC for updates to this document and the latest product status. S4804CBI Block Diagram • Provides a SONET/SDH STS-48/STM-16, 4 STS-12/STM- 4, or 16 STS-3/STM-1 line interfaces. • STS-48/STM-16 data stream supports a single STS-48c/ AU-4-16c, or any valid combination of STS-12c/AU-4-4c and/or STS-3c/AU-4 SONET/SDH payloads. • Each STS-12/STM-4 data stream supports a single STS- 12c/AU-4-4c or 4 STS-3c/AU-4 SONET/SDH payloads. • Each STS-3/STM-1 data stream supports a single STS-3c/AU-4 SONET/SDH payload. • Supports mixed STS-3 / STS-12 line rates • Provides full-duplex mapping of ATM cells or packets in each payload tributary. • Supports termination of mixed ATM and POS tributaries. • Terminates/generates SONET/SDH section, line, and path layers with transport/section E1, E2, F1, and DCC over- head interfaces in both transmit and receive directions. • APS port to support protection-switching configurations between two RHINE devices. • 16-bit, bus interface at 155 MHz for STS-48/STM-16 mode, or serial interfaces operating at 622/155 MHz for STS-12/3 (STM-4/1) modes on the line side. • 32-bit, parallel interface (FlexBus-3TM) operating at 100 MHz on the system side. • .25 micron, 2.5V core, and 3.3V tolerant I/O. • Packaged in a 624 Pin CBGA. The S4804 is a highly-integrated VLSI device that provides full-duplex mapping of packets or ATM cells to SONET/SDH payloads. It provides support for both uni-directional and bi-directional rings. The S4804 provides full section, line, and path overhead processing, and supports framing, scrambling/descrambling, alarm signal insertion/detection, and bit-interleaved parity (B1/B2/B3) processing. The S4804 is SONET/SDH standards compliant with Bellcore GR-253, ITU G.707, ITU-T 432.1, ANSI T1.105 -1995, and IETF RFCs 1619/1661/1662/2615. A general purpose 8-bit or 16-bit microprocessor interface is provided for control and monitoring. The interface supports both IntelTM and MotorolaTM type microprocessors, and is capable of operating in either an interrupt-driven or polled-mode configuration. In addition, a standard 5 signal IEEE 1149.1 JTAG Test Port is provided for Boundary Scan test purposes. Applications • ATM switches • Packet over SONET Routers and Switches • SONET/SDH Add Drop Multiplexers, Terminal Multiplexers, and Digital Cross Connects • Test equipment TX_SYS_DAT[31:0] TX_ADR[4:0] TX_CLK[1:4] TX_PRTY[1:4] TX_ENB[1:4] TX_SOC/P[1:4] TX_CLAV_PDA[1:4] RX_SYS_DAT[31:0] RX_ADR[4:0] RX_CLK[1:4] RX_PRTY[1:4] RX_ENB[1:4] RX_SOC/P[1:4] RX_CLAV_PDA[1:4] POH MON. TOH EXTRACT TOH MON. RX FRAMER TX FRAMER TOH INSERT SPE/VC GEN. RX_DV[1:4] RX_LBYTE[1:0] RX_EOP[1:4] RX_ERR[1:4] TX_EOP[1:4] TX_ERR[1:4] MICROPROCESSOR I/F JTAG PORT GPIO/LED REG TX_DATA[15:0] TX_SONETCLK_IN TX_FRAME_IN RX_DATA[15:0] RX_SONETCLK[1:16] RX_LOSEXT[1:16] RX FIFO x16 RX ATM/ HDLC CNTRS x16 TX FIFO x16 x16 x16 x16 x16 x16 x16 TX_LBYTE[1:0] TX ATM/HDLC PROC w/ SCRMBL (X43 + 1) x16 RX ATM/HDLC PROC w/ (X43 + 1) DeSCRMBL x16 TX_SONETCLK_OUT_155_622 TX_SONETCLK_OUT_155 TX_CLK_OUT[1:4] RX_CLK_OUT[1:4} RX_REF_CLK_OUT Ptr Proc Ptr Intrp x16 |
Ähnliche Teilenummer - CS4804 |
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Ähnliche Beschreibung - CS4804 |
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