Datenblatt-Suchmaschine für elektronische Bauteile |
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AD9889A Datenblatt(PDF) 5 Page - Analog Devices |
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AD9889A Datenblatt(HTML) 5 Page - Analog Devices |
5 / 12 page AD9889A Rev. 0 | Page 5 of 12 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A B C D E F G J H K 10 8 7 6 3 2 1 95 4 BOTTOM VIEW (Not to Scale) Figure 2. 76-Ball BGA Configuration (Top View) Table 3. Pin Function Descriptions Pin No. Mnemonic Type1 Description A1 to A10, B1 to B10, C9, C10, D9, D10 D[23:0] I Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from 1.8 V to 3.3 V. D1 CLK I Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V. C2 DE I Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V. C1 HSYNC I Horizontal SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V. D2 VSYNC I Vertical SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V. J3 EXT_SW I Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this pin and ground. K3 HPD I Hot Plug Detect Signal. This indicates to the interface whether the receiver is connected. 1.8 V to 5.0 V CMOS logic level. E2 S/PDIF I S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a Sony/Philips digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V. E1 MCLK I Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (fS), 256 × fS, 384 × fS, or 512 × fS. 1.8 V to 3.3 V CMOS logic level. F2, F1, G2, G1 I2S[3:0] I I2S Audio Data Inputs. These represent the eight channels of audio (two per input) available through I2S. Supports CMOS logic levels from 1.8 V to 3.3 V. H2 SCLK I I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V. H1 LRCLK I Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V. J7 PD/A0 I Power-Down Control and I2C Address Selection. The I2C address and the PD polarity are set by the PD/A0 pin state when the supplies are applied to the AD9889A. 1.8 V to 3.3 V CMOS logic level. K1, K2 TxC−/TxC+ O Differential Clock Output. Differential clock output at pixel clock rate; transition minimized differential signaling (TMDS) logic level. K10, J10 Tx2−/Tx2+ O Differential Output Channel 2. Differential output of the red data at 10× the pixel clock rate; TMDS logic level. K7, K8 Tx1−/Tx1+ O Differential Output Channel 1. Differential output of the green data at 10× the pixel clock rate; TMDS logic level. K4, K5 Tx0−/Tx0+ O Differential Output Channel 0. Differential output of the blue data at 10× the pixel clock rate; TMDS logic level. H10 INT O Interrupt. CMOS logic level. A 2 kΩ pull up resistor to interrupt the microcontroller IO supply is recommended. J2, J5, J8, K9 AVDD P 1.8 V Power Supply for TMDS Outputs. D5, D6, D7, E7 DVDD P 1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to the digital logic and I/Os. They should be filtered and as quiet as possible. G4, G5, J1 PVDD P 1.8 V PLL Power Supply. The most sensitive portion of the AD9889A is the clock generation circuitry. These pins provide power to the clock PLL. The designer should provide quiet, noise-free power to these pins. D4, E4, F4, J4, G6, J6, K6, F7, G7, H9, J9 GND P Ground. The ground return for all circuitry on-chip. It is recommended that the AD9889A be assembled on a single, solid ground plane with careful attention given to ground current paths. |
Ähnliche Teilenummer - AD9889A |
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Ähnliche Beschreibung - AD9889A |
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