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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADF4108BRUZ-RL7 Datenblatt(PDF) 10 Page - Analog Devices |
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ADF4108BRUZ-RL7 Datenblatt(HTML) 10 Page - Analog Devices |
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10 / 20 page  ADF4108 Rev. 0 | Page 10 of 20 HI HI D1 D2 Q1 Q2 CLR2 CP U1 U2 UP DOWN ABP2 ABP1 CPGND U3 R DIVIDER PROGRAMMABLE DELAY N DIVIDER VP CHARGE PUMP CLR1 Figure 14. PFD Simplified Schematic and Timing (in Lock) MUXOUT AND LOCK DETECT The output multiplexer on the ADF4108 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Figure 19 shows the full truth table. Figure 15 shows the MUXOUT section in block diagram form. Lock Detect MUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect. Digital lock detect is active high. When the lock detect precision (LDP) bit in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector (PD) cycles is less than 15 ns. With LDP set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. It will stay set high until a phase error of greater than 25 ns is detected on any subsequent PD cycle. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected, this output will be high with narrow, low-going pulses. DGND DVDD CONTROL MUX ANALOG LOCK DETECT DIGITAL LOCK DETECT R COUNTER OUTPUT N COUNTER OUTPUT SDOUT MUXOUT Figure 15. MUXOUT Circuit INPUT SHIFT REGISTER The ADF4108 digital section includes a 24-bit input shift register, a 14-bit R counter, and a 19-bit N counter, comprising a 6-bit A counter and a 13-bit B counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the 2 LSBs, DB1 and DB0, as shown in the timing diagram of Figure 2. The truth table for these bits is shown in Table 5. Figure 16 shows a summary of how the latches are programmed. Table 5. C2 and C1 Truth Table Control Bits C2 C1 Data Latch 0 0 R counter 0 1 N counter (A and B) 1 0 Function latch (Including prescaler) 1 1 Initialization latch |
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