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AM29PDL129H53 Datenblatt(PDF) 3 Page - SPANSION

Teilenummer AM29PDL129H53
Bauteilbeschribung  128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control and Dual chip Enable
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Publication Number: 26842
Rev: B Amendment/ +3
Issue Date: November 2, 2005
Am29PDL129H
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode
Simultaneous Read/Write Flash Memory with Enhanced
VersatileIOTM Control and Dual Chip Enable Inputs
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■ 128 Mbit Page Mode device
— Page size of 8 words: Fast page read access from random
locations within the page
■ Dual Chip Enable inputs
— Two CE# inputs control selection of each half of the memory
space
■ Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and program
operations for battery-powered applications
■ Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
■ FlexBank Architecture
— 4 separate banks, with up to two simultaneous operations
per device
— Bank 1A: 48 Mbit (32 Kw x 96)
— Bank 1B: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
— Bank 2A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
— Bank 2B: 48 Mbit (32 Kw x 96)
■ Enhanced VersatileI/OTM (VIO) Control
— Output voltage generated and input voltages tolerated on all
control inputs and I/Os is determined by the voltage on the
VIO pin
—VIO options at 1.8 V and 3 V I/O
■ SecSiTM (Secured Silicon) Sector region
— Up to 128 words accessible through a command sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
■ Both top and bottom boot blocks in one device
■ Manufactured on 0.13 µm process technology
■ 20-year data retention at 125°C
■ Minimum 1 million erase cycle guarantee per sector
PERFORMANCE CHARACTERISTICS
■ High Performance
— Page access times as fast as 20 ns
— Random access times as fast as 55 ns
■ Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 15 mA program/erase current
— 1 µA typical standby mode current
SOFTWARE FEATURES
■ Software command-set compatible with JEDEC 42.4
standard
— Backward compatible with Am29F and Am29LV families
■ CFI (Common Flash Interface) complaint
— Provides device-specific information to the system, allowing
host software to easily reconfigure for different Flash devices
■ Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
operations in other sectors of same bank
■ Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or erase
cycle completion
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array data
■ WP#/ACC (Write Protect/Acceleration) input
—At VIL, hardware level protection for the first and last two 4K
word sectors.
—At VIH, allows removal of sector protection
—At VHH, provides accelerated programming in a factory
setting
■ Persistent Sector Protection
— A command sector protection method to lock combinations
of individual sectors and sector groups to prevent program or
erase operations within that sector
— Sectors can be locked and unlocked in-system at VCC level
■ Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using
a user-defined 64-bit password
■ Package options
— 80-ball Fine-pitch BGA
— Multi Chip Packages (MCP)
This product has been retired and is not available for designs. For new and current designs, S29PL129J supersedes Am29PDL129H and is the factory-recom-
mended migration path. Please refer to the S29PL129J datasheet for specifications and ordering information. Availability of this document is retained for reference
and historical purposes only.


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