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DESCRIPTION/ORDERING INFORMATION

SN74SSTU32864C

25-BIT CONFIGURABLE REGISTERED BUFFER

WITH SSTL_18 INPUTS AND OUTPUTS

SCES542A – JANUARY 2004 – REVISED FEBRUARY 2005

•

Differential Clock (CLK and CLK) Inputs

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Member of the Texas Instruments Widebus+™

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Supports LVCMOS Switching Levels on

Family

Control and RESET Inputs

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Pinout Optimizes DDR2 DIMM PCB Layout

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RESET Input Disables Differential Input

Receivers, Resets All Registers, and Forces

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Configurable as 25-Bit 1:1 or 14-Bit 1:2

All Outputs Low

Registered Buffer

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Latch-Up Performance Exceeds 100 mA Per

•

Chip-Select Inputs Gate Data Outputs From

JESD 78, Class II

Changing State and Minimize System Power

Consumption

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ESD Protection Exceeds JESD 22

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Output Edge-Control Circuitry Minimizes

– 2000-V Human-Body Model (A114-A)

Switching Noise in Unterminated Line

– 200-V Machine Model (A115-A)

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Supports SSTL_18 Data Inputs

– 1000-V Charged-Device Model (C101)

pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout

configuration, two devices per DIMM are required to drive 18 SDRAM loads.

All inputs are SSTL_18, except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are

edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.

The SN74SSTU32864C operates from a differential clock (CLK and CLK). Data are registered at the crossing of

CLK going high and CLK going low.

The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to

register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to

14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to

a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the

A6, D6, and H6 terminals are driven low and should not be used.

In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and

CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is

cleared and the data outputs are driven low quickly, relative to the time to disable the differential input receivers.

However, when coming out of reset, the register becomes active quickly, relative to the time required to enable

the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the

low-to-high transition of RESET until the input receivers are fully enabled, the design of the SN74SSTU32864C

must ensure that the outputs remain low, thus ensuring no glitches on the output.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the

low state during power up.

ORDERING INFORMATION

ORDERABLE PART NUMBER

TOP-SIDE MARKING

LFBGA – GKE

Tape and reel

SN74SSTU32864CGKER

S864C

0

°C to 70°C

LFBGA – ZKE

Tape and reel

SN74SSTU32864CZKER

S864C

(1)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus+ is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 2004–2005, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.