CS5421

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9

to its high saturation flux density and have low loss at high

frequencies, a distributed gap and exhibit very low EMI.

The minimum value of inductance which prevents

inductor saturation or exceeding the rated FET current can

be calculated as follows:

LMIN +

(VIN(MIN) * VOUT)VOUT

fSW

VIN(MIN)

ISW(MAX)

where:

The inductor ripple current can then be determined:

DIL +

VOUT

(1.0 * D)

L

fSW

where:

L = inductor value;

D = duty cycle.

The designer can now verify if the number of output

capacitors will provide an acceptable output voltage ripple

(1.0% of output voltage is common). The formula below is

used:

DIL + D

VOUT

ESRMAX

Rearranging we have:

ESRMAX + D

VOUT

DIL

where:

voltage ripple ( budgeted by the designer );

The number of output capacitors is determined by:

Number of capacitors +

ESRCAP

ESRMAX

where:

manufacturer’s data sheet).

The designer must also verify that the inductor value

yields reasonable inductor peak and valley currents (the

inductor current is a triangular waveform):

IL(PEAK) + IOUT )

DIL

2.0

where:

IL(VALLEY) + IOUT *

DIL

2.0

where:

Selection of the Output Capacitors

These components must be selected and placed carefully

to yield optimal results. Capacitors should be chosen to

provide acceptable ripple on the regulator output voltage.

Key specifications for output capacitors are their ESR

(Equivalent Series Resistance), and ESL (Equivalent Series

Inductance). For best transient response, a combination of

low value/high frequency and bulk capacitors placed close

to the load will be required.

In order to determine the number of output capacitors the

maximum voltage transient allowed during load transitions

has to be specified. The output capacitors must hold the

output voltage within these limits since the inductor current

can not change with the required slew rate. The output

capacitors must therefore have a very low ESL and ESR.

The voltage change during the load current transient is:

DVOUT + DIOUT

ESL

Dt )

ESR )

tTR

COUT

where:

Δt = load transient duration time;

ESL = Maximum allowable ESL including capacitors,

circuit traces, and vias;

ESR = Maximum allowable ESR including capacitors

and circuit traces;

The designer has to independently assign values for the

change in output voltage due to ESR, ESL, and output

capacitor discharging or charging. Empirical data indicates

that most of the output voltage change (droop or spike

depending on the load current transition) results from the

total output capacitor ESR.

The maximum allowable ESR can then be determined

according to the formula:

ESRMAX +

DVESR

DIOUT

where:

by the designer)

Once the maximum allowable ESR is determined, the

number of output capacitors can be found by using the

formula:

Number of capacitors +

ESRCAP

ESRMAX

where:

manufacturer’s data sheet).

ESR = maximum allowable ESR.

The actual output voltage deviation due to ESR can then

be verified and compared to the value assigned by the

designer: