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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADSP-BF538BBCZ-4F4 Datenblatt(PDF) 7 Page - Analog Devices |
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ADSP-BF538BBCZ-4F4 Datenblatt(HTML) 7 Page - Analog Devices |
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7 / 56 page  ADSP-BF538/ADSP-BF538F Preliminary Technical Data Rev. PrD | Page 7 of 56 | May 2006 • Non-maskable interrupt (NMI) – The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. • Exceptions – Events that occur synchronously to program flow (the exception are taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. • Interrupts – Events that occur asynchronously to program flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processors are saved on the supervisor stack. The ADSP-BF538/ADSP-BF538F processor’s event controllers consist of two stages, the core event controller (CEC) and the system interrupt controller (SIC). the core event controller works with the system interrupt controller to prioritize and con- trol all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CEC. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest priority inter- rupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the processor. Table 2 describes the inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities. System Interrupt Controllers (SIC) The system interrupt controllers (SIC0, SIC1) provide the map- ping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF538/ADSP-BF538F processors provide a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (IAR). Table 3 describes the inputs into the SICs and the default mappings into the CEC. Table 2. Core Event Controller (CEC) Priority (0 is Highest) Event Class EVT Entry 0Emulation/Test Control EMU 1 Reset RST 2 Non-Maskable Interrupt NMI 3Exception EVX 4 Reserved — 5 Hardware Error IVHW 6 Core Timer IVTMR 7 General Interrupt 7 IVG7 8 General Interrupt 8 IVG8 9 General Interrupt 9 IVG9 10 General Interrupt 10 IVG10 11 General Interrupt 11 IVG11 12 General Interrupt 12 IVG12 13 General Interrupt 13 IVG13 14 General Interrupt 14 IVG14 15 General Interrupt 15 IVG15 Table 3. System and Core Event Mapping Event Source Core Event Name PLL Wakeup Interrupt IVG7 DMA Controller 0 Error IVG7 DMA Controller 1 Error IVG7 PPI Error Interrupt IVG7 SPORT0 Error Interrupt IVG7 SPORT1 Error Interrupt IVG7 SPORT2 Error Interrupt IVG7 SPORT3 Error Interrupt IVG7 SPI0 Error Interrupt IVG7 SPI1 Error Interrupt IVG7 SPI2 Error Interrupt IVG7 UART0 Error Interrupt IVG7 UART1 Error Interrupt IVG7 UART2 Error Interrupt IVG7 CAN Error Interrupt IVG7 Real Time Clock Interrupts IVG8 DMA0 Interrupt (PPI) IVG8 DMA1 Interrupt (SPORT0 RX) IVG9 DMA2 Interrupt (SPORT0 TX) IVG9 DMA3 Interrupt (SPORT1 RX) IVG9 DMA4 Interrupt (SPORT1 TX) IVG9 DMA8 Interrupt (SPORT2 RX) IVG9 DMA9 Interrupt (SPORT2 TX) IVG9 DMA10 Interrupt (SPORT3 RX) IVG9 DMA11 Interrupt (SPORT3 TX) IVG9 DMA5 Interrupt (SPI0) IVG10 DMA14 Interrupt (SPI1) IVG10 DMA15 Interrupt (SPI2) IVG10 DMA6 Interrupt (UART0 RX) IVG10 DMA7 Interrupt (UART0 TX) IVG10 DMA16 Interrupt (UART1 RX) IVG10 DMA17 Interrupt (UART1 TX) IVG10 |
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