Datenblatt-Suchmaschine für elektronische Bauteile |
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ADT7462 Datenblatt(PDF) 5 Page - Analog Devices |
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ADT7462 Datenblatt(HTML) 5 Page - Analog Devices |
5 / 92 page ADT7462 Rev. 0 | Page 5 of 92 Parameter Min Typ Max Unit Test Conditions/Comments SERIAL BUS DIGITAL INPUTS (SDA AND SCL) Input High Voltage, VIH 2.1 V Input Low Voltage, VIL 0.4 V Hysteresis 500 mV DIGITAL INPUT LOGIC LEVELS (VID0 to VID6) AND THERM, TACH, GPIO, VR_HOT, SCSI_TERM) Input High Voltage, VIH 1.7 V Bit 3 and Bit 4 of Configuration Register 3 = 0 Input Low Voltage, VIL 0.8 V Bit 3 and Bit 4 of Configuration Register 3 = 0 Input High Voltage, VIH (VID0 to VID6) 0.65 V Bit 3 of Configuration Register 3 = 1 Input High Voltage, VIH (THERM) 2/3 VCCP1 V Bit 4 of Configuration Register 3 = 1 Input Low Voltage, VIL 0.4 V Bit 3 and Bit 4 of Configuration Register 3 = 1 Hysteresis 500 mV DIGITAL INPUT CURRENTS Input High Current, IIH −1 μA VIN = VCC Input Low Current, IIL +1 μA VIN = 0 Input Capacitance3 5 pF SERIAL BUS TIMING3 Clock Frequency 400 kHz See Figure 2 Glitch Immunity, tSW 50 ns See Figure 2 Bus Free Time 1.3 μs See Figure 2 Start Setup Time, tSU;STA 0.6 μs See Figure 2 Start Hold Time, tHD;STA 0.6 μs See Figure 2 SCL Low Time, tLOW 1.3 μs See Figure 2 SCL High Time, tHIGH 0.6 μs See Figure 2 SCL, SDA Rise Time, tr 1000 ns See Figure 2 SCL, SDA Fall Time, tF 300 ns See Figure 2 Data Setup Time, tSU;DAT 100 ns See Figure 2 Detect Clock Low Timeout 25 ms Can be optionally enabled 1 All voltages are measured with respect to GND, unless otherwise specified. Typical values are at TA = 25°C and represent the most likely parametric norm. Logic inputs accept input high voltages up to 5 V, even when the device is operating at supply voltages below 5 V. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge. 2 Unused digital inputs connected to GND. 3 Guaranteed by design, not production tested. 4 Note that this specification does not apply if Pin 26 (VBATT, +1.2V) is being measured in single-channel mode. See Figure 22 in Typical Performance Characteristics for VBATT accuracy. 5 For Pin 23 and Pin 24 configured as +1.8V or +2.5V only, restricted conditions of VCC ≥ 3.3 V and +25°C ≤ TA ≤ +125°C apply. TIMING DIAGRAM SCL SDA PS S P tSU;STO tHD;STA tSU;STA tSU;DAT tHD;DAT tHD;STA tHIGH tBUF tLOW tR tF Figure 2. Serial Bus Timing Diagram |
Ähnliche Teilenummer - ADT7462 |
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Ähnliche Beschreibung - ADT7462 |
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