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AD7641BSTZRL Datenblatt(PDF) 8 Page - Analog Devices

Teilenummer AD7641BSTZRL
Bauteilbeschribung  18-Bit 250/670 kSPS PulSAR Bipolar Programmable Inputs ADC
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Direct Link  http://www.analog.com
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AD7641BSTZRL Datenblatt(HTML) 8 Page - Analog Devices

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AD7631/AD7634
Preliminary Technical Data
Rev. PrC | Page 8 of 14
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Analog Inputs/Outputs
IN+, IN−, REF, REFBUFIN, TEMP,
INGND, REFGND to AGND
AVDD + 0.3 V to
AGND − 0.3 V
Ground Voltage Differences
AGND, DGND, OGND
±0.3 V
Supply Voltages
AVDD, DVDD
−0.3 V to +2.7 V
OVDD
−0.3 V to +3.8 V
AVDD to DVDD
±2.8 V
AVDD, DVDD to OVDD
−3.8 V to +2.8 V
Digital Inputs
−0.3 V to +5.5 V
PDREF, PDBUF
±20 mA
Internal Power Dissipation
700 mW
1
Internal Power Dissipation
2.5 W
2
Junction Temperature
125°C
Storage Temperature Range
–65°C to +125°C
1. Specification is for the device in free air:
48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W.
2. Specification is for the device in free air:
48-Lead LFCSP; θJA = 26°C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
500µAIOL
500µAIOH
1.4V
TO OUTPUT
PIN
CL
50pF
0.8V
2V
2V
0.8V
0.8V
2V
tDELAY
tDELAY
Figure 3. Voltage Reference Levels for Timing
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, C = 10 pF
L


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