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74AUP1G240GW Datenblatt(PDF) 2 Page - NXP Semiconductors |
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74AUP1G240GW Datenblatt(HTML) 2 Page - NXP Semiconductors |
2 / 19 page 74AUP1G240_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 6 November 2006 2 of 19 NXP Semiconductors 74AUP1G240 Low-power inverting buffer/line driver; 3-state s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from −40 °Cto+85 °C and −40 °C to +125 °C 3. Ordering information 4. Marking 5. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G240GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74AUP1G240GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm SOT886 74AUP1G240GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1 × 0.5 mm SOT891 Table 2. Marking Type number Marking code 74AUP1G240GW p2 74AUP1G240GM p2 74AUP1G240GF p2 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 001aac528 OE AY 1 24 001aac527 OE 1 2 4 001aac526 Y A OE |
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