AD7796BRUZ datasheet(5/24 Pages) AD

Teilenummer	AD7796BRUZ

Bauteilbeschribung	Low Power, 16-/24-Bit Sigma-Delta ADC for Bridge Sensors

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Hersteller	AD [Analog Devices]

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AD7796/AD7797

Rev. A | Page 5 of 24

TIMING CHARACTERISTICS

AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.

Table 2.

Parameter1, 2

Limit at TMIN, TMAX (B Version)

Unit

Conditions/Comments

t3

100

ns min

SCLK high pulse width

t4

100

ns min

SCLK low pulse width

Read Operation

t1

0

ns min

CS falling edge to DOUT/RDY active time

60

ns max

DVDD = 4.75 V to 5.25 V

80

ns max

DVDD = 2.7 V to 3.6 V

t23

0

ns min

SCLK active edge to data valid delay4

60

ns max

DVDD = 4.75 V to 5.25 V

80

ns max

DVDD = 2.7 V to 3.6 V

t55, 6

10

ns min

Bus relinquish time after CS inactive edge

80

ns max

t6

0

ns min

SCLK inactive edge to CS inactive edge

t7

10

ns min

SCLK inactive edge to DOUT/RDY high

Write Operation

t8

0

ns min

CS falling edge to SCLK active edge setup time4

t9

30

ns min

Data valid to SCLK edge setup time

t10

25

ns min

Data valid to SCLK edge hold time

t11

0

ns min

CS rising edge to SCLK edge hold time

1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2 See Figure 3 and Figure 4.

3 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4 SCLK active edge is falling edge of SCLK.

5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus

relinquish times of the parts and, as such, are independent of external bus loading capacitances.

6

RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high.

Care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.

ISINK (1.6mA WITH DVDD =5V,

100µAWITHDVDD =3V)

ISOURCE (200µA WITH DVDD =5V,

100µAWITHDVDD =3V)

1.6V

TO

OUTPUT

50pF

Figure 2. Load Circuit for Timing Characterization

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