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ISL12026IBZ Datenblatt(PDF) 5 Page - Intersil Corporation

Teilenummer ISL12026IBZ
Bauteilbeschribung  Real Time Clock/Calendar with EEPROM
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Hersteller  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL12026IBZ Datenblatt(HTML) 5 Page - Intersil Corporation

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5
FN8231.5
October 23, 2006
Timing Diagrams
Bus Timing
Write Cycle Timing
tHD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL
falling edge. Both crossing 70%
of VDD.
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing
30% of VDD, until SDA enters the
30% to 70% of VDD window.
0ns
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip.
10
400
pF
Cpin
SDA, and SCL Pin Capacitance
10
pF
tWC
Non-volatile Write Cycle Time
12
20
ms
10
NOTES:
3. IRQ/FOUT Inactive.
4. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz
5. VDD > VBAT +VBATHYS
6. Bit BSW = 0 (Standard Mode), VBAT >= 1.8V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
9. Parameter is not 100% tested.
10. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
AC Electrical Specifications
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
tSU:STO
tDH
tHIGH
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tF
tLOW
tBUF
tAA
tR
tHD:STO
SCL
SDA
tWC
8TH BIT OF LAST BYTE
ACK
STOP
CONDITION
START
CONDITION
ISL12026


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