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2BI

1BI

10AI1

10AI2

GTL INPUT 11BI

11BO GTL OUTPUT

10BO2

10BO1

4AO

3AO

2AO

1AO

LVTTL I/O

5BI

LVTTL I/O 11A (OPEN DRAIN)

5A (OPEN DRAIN)

6A (OPEN DRAIN)

7BO1

1

2

3

4

5

6

26

25

24

22

21

20

19

18

17

16

15

8

9

10

11

12

13

SN74GTL2107

27

LVTTL INPUT EN1

GTL INPUT 9BI

7BO2

6BI

EN2 LVTTL INPUT

23

3BI

4BI

9AO LVTTL OUTPUT

7

GTL

INPUTS

GTL

INPUTS

GTL

OUTPUTS

LVTTL INPUTS

LVTTL OD OUTPUTS

LVTTL OD OUTPUTS

GTL

OUTPUTS

SN74GTL2107

12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR

SCLS699 – JULY 2006

LOGIC SYMBOL

(1)

The enable on 7BO1/7BO2 includes a delay that prevents a transient condition (where 5BI/6BI go from low to high,

and the low to high on 5A/6A lags up to 100 ns) from causing a low glitch on the 7BO1/7BO2 outputs.

3

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