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ST62T30B Datenblatt(PDF) 5 Page - STMicroelectronics |
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ST62T30B Datenblatt(HTML) 5 Page - STMicroelectronics |
5 / 84 page 5/84 ST62T30B ST62E30B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62T30B and ST62E30B devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to me- dium complexity applications. All ST62xx devices are based on a building block approach: a com- mon core is surrounded by a number of on-chip peripherals. The ST62E30B is the erasable EPROM version of the ST62T30B device, which may be used to em- ulate the ST62T30B device, as well as the respec- tive ST6230B ROM devices. Figure 1. Block Diagram TEST NMI INTERRUPT PROGRAM PC STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 POWER SUPPLY OSCILLATOR RESET DATA ROM USER SELECTABLE DATA RAM PORT A PORT B TIMER DIGITAL 8 BIT CORE TEST/VPP 8-BIT A/D CONVERTER PA0..PA1 / 20 mA Sink VDD VSS OSCin OSCout RESET WATCHDOG Memory PORT C SPI (SERIAL PERIPHERAL INTERFACE) AUTORELOAD TIMER 192 Bytes 7948 bytes DATA EEPROM 128 Bytes PA2/OVF/ 20 mA Sink PA3/PWM/20 mA Sink PA4/Ain/CP1 PA5/Ain/CP2 PB4..PB6/Ain PC4..PC7/Ain PORT D PD6,PD7/Ain PD1/Ain/Scl PD2/Ain/Sin PD3/Ain/Sout PD4/Ain/RXD1 PD5/Ain/TXD1 (VPP on EPROM/OTP versions only) TIMER VR01823F UART |
Ähnliche Teilenummer - ST62T30B_03 |
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Ähnliche Beschreibung - ST62T30B_03 |
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