Datenblatt-Suchmaschine für elektronische Bauteile |
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CDC906PWRG4 Datenblatt(PDF) 5 Page - Texas Instruments |
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CDC906PWRG4 Datenblatt(HTML) 5 Page - Texas Instruments |
5 / 39 page www.ti.com RECOMMENDED OPERATING CONDITIONS RECOMMENDED CRYSTAL SPECIFICATIONS TIMING REQUIREMENTS CDC906 SCAS828 – SEPTEMBER 2006 over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Device supply voltage 3 3.3 3.6 V VCCOUT1 Output Y0,Y1 supply voltage 2.3 3.6 V VCCOUT2 Output Y2, Y3, Y4, Y5 supply voltage 2.3 3.6 V VIL Low level input voltage LVCMOS 0.3 VCC V VIH High level input voltage LVCMOS 0.7 VCC V VIthresh Input voltage threshold LVCMOS 0.5 VCC V VI Input voltage range LVCMOS 0 3.6 V |VID| Differential input voltage 0.1 V VIC Common-mode for differential input voltage 0.2 VCC– 0.6 V IOH / IOL Output current (3.3 V) ±6 mA IOH / IOL Output current (2.5 V) ±4 mA CL Output load LVCMOS 25 pF TA Operating free-air temperature 0 70 °C MIN NOM MAX UNIT fXtal Crystal input frequency range (fundamental mode) 8 27 54 MHz ESR Effective series resistance(1)(2) 15 60 Ω CIN Input capacitance CLK_IN0 and CLK_IN1 3 pF (1) For crystal frequencies above 50 MHz the effective series resistor should not exceed 50 Ω to assure stable start-up condition. (2) Maximum Power Handling (Drive Level) see Figure 16. over recommended ranges of supply voltage, load, and operating-free air temperature MIN NOM MAX UNIT CLK_IN REQUIREMENTS PLL mode 1 167 fCLK_IN CLK_IN clock input frequency (LVCMOS or Differential) MHz PLL bypass mode 0 167 tr / tf Rise and fall time CLK_IN signal (20% to 80%) 4 ns dutyREF Duty cycle CLK_IN at VCC / 2 40% 60% SMBus TIMING REQUIREMENTS (see Figure 11) fSCLK SCLK frequency 100 kHz th(START) START hold time 4 µs tw(SCLL) SCLK low-pulse duration 4.7 µs tw(SCLH) SCLK high-pulse duration 4 50 µs tsu(START) START setup time 0.6 µs th(SDATA) SDATA hold time 0.3 µs tsu(SDATA) SDATA setup time 0.25 µs tr SCLK / SDATA input rise time 1000 ns tf SCLK / SDATA input fall time 300 ns tsu(STOP) STOP setup time 4 µs tBUS Bus free time 4.7 µs tPOR Time in which the device must be operational after power-on reset 500 ms 5 Submit Documentation Feedback |
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