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CDC906PWRG4 Datenblatt(PDF) 7 Page - Texas Instruments |
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CDC906PWRG4 Datenblatt(HTML) 7 Page - Texas Instruments |
7 / 39 page www.ti.com CDC906 SCAS828 – SEPTEMBER 2006 DEVICE CHARACTERISTICS (continued) over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1 PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT odc Output duty cycle(8) f(VCO) = 100 MHz, Pdiv = 1 45% 55% LVCMOS PARAMETER FOR VCCOUT = 2.5-V Mode VCCOUT = 2.3 V, IOH = 0.1 mA 2.2 VOH LVCMOS high-level output voltage VCCOUT = 2.3 V, IOH = –3 mA 1.7 V VCCOUT = 2.3 V, IOH = –4 mA 1.5 VCCOUT = 2.3 V, IOL = 0.1 mA 0.1 VOL LVCMOS low-level output voltage VCCOUT = 2.3 V, IOL = 3 mA 0.5 V VCCOUT = 2.3 V, IOL = 4 mA 0.85 All PLL bypass 9 tPLH, Propagation delay ns tPHL VCO bypass 11 tr0/tf0 Rise and fall time for output slew rate 0 VCCOUT = 2.5 V (20%–80%) 2 3.9 5.6 ns tr1/tf1 Rise and fall time for output slew rate 1 VCCOUT = 2.5 V (20%–80%) 1.8 2.9 4.4 ns tr2/tf2 Rise and fall time for output slew rate 2 VCCOUT = 2.5 V (20%–80%) 1.3 2 3.2 ns Rise and fall time for output slew rate 3 tr3/tf3 VCCOUT = 2.5 V (20%–80%) 0.4 0.8 1.1 ns (Default Configuration) 1 PLL, 1 Output fOUT = 24.576 MHz 85 120 tjit(cc) Cycle-to-cycle jitter (9)(10) ps 3 PLLs, 3 Outputs fOUT = 24.576 MHz 95 155 1 PLL, 1 Output fOUT = 24.576 MHz 110 135 tjit(per) Peak-to-peak period jitter (9)(10) ps 3 PLLs, 3 Outputs fOUT = 24.576 MHz 110 175 2-ns rise/fall time at f(VCO) = 150 MHz, tsk(o) Output skew (see (11) and Table 5) 250 ps Pdiv = 3 odc Output duty cycle(12) f(VCO) = 100 MHz, Pdiv = 1 45% 55% SMBus PARAMETER VIK SCLK and SDATA input clamp voltage VCC = 3 V, II = –18 mA –1.2 V II SCLK and SDATA input current VI = 0 V or VCC, VCC = 3.6 V ±5 µA VIH SCLK input high voltage 2.1 V VIL SCLK input low voltage 0.8 V VOL SDATA low-level output voltage IOL = 4 mA, VCC = 3 V 0.4 V CI(SCLK) Input capacitance at SCLK VI = 0 V or VCC 3 10 pF CI(SDAT Input capacitance at SDATA VI = 0 V or VCC 3 10 pF A) (8) odc depends on output rise and fall time (tr/tf); above limits are for normal tr/tf. (9) 50000 cycles. (10) Jitter depends on configuration. Jitter data is for normal tr/tf, input frequency = 27 MHz, f(VCO) = 147 MHz output. (11) The tsk(o) specification is only valid for equal loading of all outputs. (12) odc depends on output rise and fall time (tr/tf); above limits are for normal tr/tf. 7 Submit Documentation Feedback |
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