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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADSP-BF533SBB500 Datenblatt(PDF) 7 Page - Analog Devices |
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ADSP-BF533SBB500 Datenblatt(HTML) 7 Page - Analog Devices |
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7 / 60 page  ADSP-BF533 Rev. D | Page 7 of 60 | September 2006 • Exceptions – Events that occur synchronously to program flow (i.e., the exception will be taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. • Interrupts – Events that occur asynchronously to program flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. The ADSP-BF533 processor event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the sys- tem interrupt controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CEC. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest priority inter- rupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF533 processor. Table 2 describes the inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities. System Interrupt Controller (SIC) The system interrupt controller provides the mapping and rout- ing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF533 processor provides a default map- ping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (IAR). Table 3 describes the inputs into the SIC and the default mappings into the CEC. Event Control The ADSP-BF533 processor provides the user with a very flexi- ble mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide: • CEC interrupt latch register (ILAT) – The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared. • CEC interrupt mask register (IMASK) – The IMASK regis- ter controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and will be processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, pre- venting the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read or written while in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.) Figure 3. ADSP-BF533 Internal/External Memory Map RESERVED CORE MMR REGISTERS (2M BYTE) RESERVED SCRATCHPAD SRAM (4K BYTE) INSTRUCTION SRAM (64K BYTE) SYSTEM MMR REGISTERS (2M BYTE) RESERVED RESERVED DATA BANK B SRAM/CACHE (16K BYTE) DATA BANK B SRAM (16K BYTE) DATA BANK A SRAM/CACHE (16K BYTE) ASYNC MEMORY BANK 3 (1M BYTE) ASYNC MEMORY BANK 2 (1M BYTE) ASYNC MEMORY BANK 1 (1M BYTE) ASYNC MEMORY BANK 0 (1M BYTE) SDRAM MEMORY (16M BYTE TO 128M BYTE) INSTRUCTION SRAM/CACHE (16K BYTE) 0xFFFF FFFF 0xFFE0 0000 0xFFB0 0000 0xFFA1 4000 0xFFA1 0000 0xFF90 8000 0xFF90 4000 0xFF80 8000 0xFF80 4000 0xEF00 0000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0x0800 0000 0x0000 0000 0xFFC0 0000 0xFFB0 1000 0xFFA0 0000 RESERVED RESERVED DATA BANK A SRAM (16K BYTE) 0xFF90 0000 0xFF80 0000 RESERVED Table 2. Core Event Controller (CEC) Priority (0 is Highest) Event Class EVT Entry 0Emulation/Test Control EMU 1 Reset RST 2 Nonmaskable Interrupt NMI 3Exception EVX 4 Reserved 5 Hardware Error IVHW 6 Core Timer IVTMR 7 General Interrupt 7 IVG7 8 General Interrupt 8 IVG8 9 General Interrupt 9 IVG9 10 General Interrupt 10 IVG10 11 General Interrupt 11 IVG11 12 General Interrupt 12 IVG12 13 General Interrupt 13 IVG13 14 General Interrupt 14 IVG14 15 General Interrupt 15 IVG15 |
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