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ADS8472IBRGZR Datenblatt(PDF) 25 Page - Burr-Brown (TI) |
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ADS8472IBRGZR Datenblatt(HTML) 25 Page - Burr-Brown (TI) |
25 / 30 page www.ti.com LAYOUT ADS8472 SLAS514 – DECEMBER 2006 • Issue a CONVST when CS is low and the internal convert state is high. The falling edge of CONVST starts a reset. • Issue a CS (select the device) while the internal convert state is high. The falling edge of CS causes a reset. Once the device is reset, all output latches are cleared (set to zeroes) and the BUSY signal is brought low. A new sampling period is started at the falling edge of the BUSY signal immediately after the instant of the internal reset. For optimum performance, care must be taken with the physical layout of the ADS8472 circuitry. As the ADS8472 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. On average, the ADS8472 draws very little current from an external reference as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1- µF capacitor is recommended from pin 13 (REFIN) directly to pin 12 (REFM). REFM and AGND must be shorted on the same ground plane under the device. The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. Power to the ADS8472 should be clean and well bypassed. A 0.1- µF ceramic bypass capacitor should be placed as close to the device as possible. See Table 3 for the placement of the capacitor. In addition, a 1- µF to 10-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100- µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors-all designed to essentially low-pass filter the 5-V supply, removing the high frequency noise. Table 3. Power Supply Decoupling Capacitor Placement POWER SUPPLY PLANE CONVERTER CONVERTER ANALOG SIDE DIGITAL SIDE SUPPLY PINS Pin pairs that require shortest path to decoupling capacitors (7,8), (9,10), (16,17), (20,21), (22,23), (25,26) (36,37) Pins that require no decoupling 24, 26 (1,2) 25 Submit Documentation Feedback |
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