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ADSP-BF532SBSTZ400 Datenblatt(PDF) 7 Page - Analog Devices

Teilenummer ADSP-BF532SBSTZ400
Bauteilbeschribung  Blackfin Embedded Processor
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ADSP-BF532SBSTZ400 Datenblatt(HTML) 7 Page - Analog Devices

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ADSP-BF531/ADSP-BF532
Rev. D
|
Page 7 of 60
|
August 2006
• Exceptions – Events that occur synchronously to program
flow (i.e., the exception will be taken before the instruction
is allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The ADSP-BF531/ADSP-BF532 processor event controller con-
sists of two stages, the core event controller (CEC) and the
system interrupt controller (SIC). The core event controller
works with the system interrupt controller to prioritize and con-
trol all system events. Conceptually, interrupts from the
peripherals enter into the SIC, and are then routed directly into
the general-purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of theADSP-BF531/ADSP-BF532 pro-
cessor. Table 2 describes the inputs to the CEC, identifies their
names in the event vector table (EVT), and lists their priorities.
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and rout-
ing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Figure 3. ADSP-BF532 Internal/External Memory Map
Figure 4. ADSP-BF531 Internal/External Memory Map
CORE MMR REGISTERS (2M BYTE)
RESERVED
SCRATCHPAD SRAM (4K BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
RESERVED
RESERVED
DATA BANK B SRAM/CACHE (16K BYTE)
RESERVED
DATA BANK A SRAM/CACHE (16K BYTE)
ASYNC MEMORY BANK 3 (1M BYTE)
ASYNC MEMORY BANK 2 (1M BYTE)
ASYNC MEMORY BANK 1 (1M BYTE)
ASYNC MEMORY BANK 0 (1M BYTE)
SDRAM MEMORY (16M BYTE TO 128M BYTE)
INSTRUCTION SRAM/CACHE (16K BYTE)
0xFFFF FFFF
0xFFE0 0000
0xFFB0 0000
0xFFA1 4000
0xFFA0 8000
0xFF90 8000
0xFF90 4000
0xFF80 8000
0xFF80 4000
0xEF00 0000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x0800 0000
0x0000 0000
0xFFC0 0000
0xFFB0 1000
0xFFA0 0000
RESERVED
RESERVED
RESERVED
0xFFA1 0000
INSTRUCTION SRAM (32K BYTE)
RESERVED
CORE MMR REGISTERS (2M BYTE)
RESERVED
SCRATCHPAD SRAM (4K BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
RESERVED
RESERVED
RESERVED
DATA BANK A SRAM/CACHE (16K BYTE)
ASYNC MEMORY BANK 3 (1M BYTE)
ASYNC MEMORY BANK 2 (1M BYTE)
ASYNC MEMORY BANK 1 (1M BYTE)
ASYNC MEMORY BANK 0 (1M BYTE)
SDRAM MEMORY (16M BYTE TO 128M BYTE)
INSTRUCTION SRAM/CACHE (16K BYTE)
0xFFFF FFFF
0xFFE0 0000
0xFFB0 0000
0xFFA1 4000
0xFFA0 8000
0xFF90 8000
0xFF90 4000
0xFF80 8000
0xFF80 4000
0xEF00 0000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x0800 0000
0x0000 0000
0xFFC0 0000
0xFFB0 1000
0xFFA0 0000
RESERVED
RESERVED
RESERVED
0xFFA1 0000
INSTRUCTION SRAM (16K BYTE)
RESERVED
RESERVED
0xFFA0 C000
RESERVED
Table 2. Core Event Controller (CEC)
Priority
(0 is Highest)
Event Class
EVT Entry
0Emulation/Test Control
EMU
1
Reset
RST
2
Nonmaskable Interrupt
NMI
3Exception
EVX
4
Reserved
5
Hardware Error
IVHW
6Core Timer
IVTMR
7
General Interrupt 7
IVG7
8
General Interrupt 8
IVG8
9
General Interrupt 9
IVG9
10
General Interrupt 10
IVG10
11
General Interrupt 11
IVG11
12
General Interrupt 12
IVG12
13
General Interrupt 13
IVG13
14
General Interrupt 14
IVG14
15
General Interrupt 15
IVG15


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