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ADSP-BF531SBSTZ400 Datenblatt(PDF) 10 Page - Analog Devices |
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ADSP-BF531SBSTZ400 Datenblatt(HTML) 10 Page - Analog Devices |
10 / 60 page Rev. D | Page 10 of 60 | August 2006 ADSP-BF531/ADSP-BF532 TIMERS There are four general-purpose programmable timer units in the ADSP-BF531/ADSP-BF532 processor. Three timers have an external pin that can be configured either as a pulse-width mod- ulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input to the PF1 pin, an external clock input to the PPI_CLK pin, or to the internal SCLK. The timer units can be used in conjunction with the UART to measure the width of the pulses in the data stream to provide an autobaud detect function for a serial channel. The timers can generate interrupts to the processor core provid- ing periodic events for synchronization, either to the system clock or to a count of external signals. In addition to the three general-purpose programmable timers, a fourth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts. SERIAL PORTS (SPORTs) The ADSP-BF531/ADSP-BF532 processor incorporates two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features: •I2S capable operation. • Bidirectional operation – Each SPORT has two sets of inde- pendent transmit and receive pins, enabling eight channels of I2S stereo audio. • Buffered (8-deep) transmit and receive ports – Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers. • Clocking – Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (f SCLK/131,070) Hz to (fSCLK/2) Hz. • Word length – Each SPORT supports serial data words from 3 bits to 32 bits in length, transferred most-signifi- cant-bit first or least-significant-bit first. • Framing – Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. • Companding in hardware – Each SPORT can perform A-law or µ-law companding according to ITU recommen- dation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. • DMA operations with single-cycle overhead – Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory. • Interrupts – Each transmit and receive port generates an interrupt upon completing the transfer of a data-word or after transferring an entire data buffer or buffers through DMA. • Multichannel capability – Each SPORT supports 128 chan- nels out of a 1,024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards. An additional 250 mV of SPORT input hysteresis can be enabled by setting Bit 15 of the PLL_CTL register. When this bit is set, all SPORT input pins have the increased hysteresis. SERIAL PERIPHERAL INTERFACE (SPI) PORT The ADSP-BF531/ADSP-BF532 processor has an SPI-compati- ble port that enables the processor to communicate with multiple SPI-compatible devices. The SPI interface uses three pins for transferring data: two data pins (master output-slave input, MOSI, and master input-slave output, MISO) and a clock pin (serial clock, SCK). An SPI chip select input pin (SPISS) lets other SPI devices select the proces- sor, and seven SPI chip select output pins (SPISEL7–1) let the processor select other SPI devices. The SPI select pins are recon- figured programmable flag pins. Using these pins, the SPI port provides a full-duplex, synchronous serial interface which sup- ports both master/slave modes and multimaster environments. The baud rate and clock phase/polarities for the SPI port are programmable, and it has an integrated DMA controller, con- figurable to support transmit or receive data streams. The SPI DMA controller can only service unidirectional accesses at any given time. The SPI port clock rate is calculated as: Where the 16-bit SPI_Baud register contains a value of 2 to 65,535. During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sam- pling of data on the two serial data lines. UART PORT The ADSP-BF531/ADSP-BF532 processor provides a full- duplex universal asynchronous receiver/transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART port includes support for 5 data bits to 8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation: • PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. • DMA (direct memory access) – The DMA controller trans- fers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer SPI Clock Rate fSCLK 2SPI_Baud × -------------------------------- = |
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Ähnliche Beschreibung - ADSP-BF531SBSTZ400 |
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