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SN74HC175DBRE4 Datenblatt(PDF) 2 Page - Texas Instruments |
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SN74HC175DBRE4 Datenblatt(HTML) 2 Page - Texas Instruments |
2 / 16 page SN54HC175, SN74HC175 QUADRUPLE DTYPE FLIPFLOPS WITH CLEAR SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output. FUNCTION TABLE (each flip-flop) INPUTS OUTPUTS CLR CLK D Q Q L X X L H H ↑ HH L H ↑ LL H H L X Q0 Q0 logic diagram (positive logic) 1Q 9 1 C1 1D CLR CLK 1D R 1Q To Three Other Channels 4 2 3 Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC −0.5 V to 7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous output current, IO (VO = 0 to VCC) ±25 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous current through VCC or GND ±50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 2): D package 73 °C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DB package 67 °C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N package 82 °C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NS package 64 °C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PW package 108 °C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg −65 °C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. |
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