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SN74GTL16616DLRG4 Datenblatt(PDF) 2 Page - Texas Instruments |
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SN74GTL16616DLRG4 Datenblatt(HTML) 2 Page - Texas Instruments |
2 / 14 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCBS481H – JUNE 1994 – REVISED APRIL 2005 The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port. VCC (5 V) supplies the internal and GTL circuitry, while VCC (3.3 V) supplies the LVTTL output buffers. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CEBA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE(1) INPUTS OUTPUT MODE B CEAB OEAB LEAB CLKAB A X H X X X Z Isolation L L L H X B0(2) Latched storage of A data L L L L X B0(3) X L H X L L Transparent X L H X H H L L L ↑ L L Clocked storage of A data L L L ↑ H H H L L X X B0(3) Clock inhibit (1) A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA, and CEBA. The condition when OEAB and OEBA are both low at the same time is not recommended. (2) Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low (3) Output level before the indicated steady-state input conditions were established 2 |
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Ähnliche Beschreibung - SN74GTL16616DLRG4 |
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