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2

Unit Loading/Fan Out

Functional Description

The 16-bit shift register operates in one of three modes, as

indicated in the Shift Register Operations Table.

HOLD— a HIGH signal on the Chip Select (CS) input pre-

vents clocking, and data is stored in the sixteen registers.

Shift/Serial Load— data present on the SI pin shifts into

appearing on the SO pin.

the register on the falling edge of CP. The SO output repre-

To prevent false clocking, CP must be LOW during a

LOW-to-HIGH transition of CS.

Shift Register Operations Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

 = HIGH-to-LOW Transition

Block Diagram

Pin Names

Description

U.L.

HIGH/LOW

Parallel Data Inputs

1.0/1.0

20

µA/−0.6 mA

CS

Chip Select Input (Active LOW)

1.0/1.0

20

µA/−0.6 mA

CP

Clock Pulse Input (Active LOW)

1.0/1.0

20

µA/−0.6 mA

M

Mode Select Input

1.0/1.0

20

µA/−0.6 mA

SI

Serial Data Input

1.0/1.0

20

µA/−0.6 mA

SO

Serial Output

50/33.3

−1 mA/20 mA

Control Input

Operating Mode

CS

MCP

HX

X

Hold

LL



Shift/Serial Load

LH



Parallel Load