Datenblatt-Suchmaschine für elektronische Bauteile |
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AD8324 Datenblatt(PDF) 1 Page - Analog Devices |
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AD8324 Datenblatt(HTML) 1 Page - Analog Devices |
1 / 16 page 3.3 V Upstream Cable Line Driver AD8324 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. FEATURES Supports DOCSIS 2.0 and Euro-DOCSIS standards for reverse path transmission systems Gain programmable in 1 dB steps over a 59 dB range Low distortion at 61 dBmV output: –59 dBc SFDR at 21 MHz –54 dBc SFDR at 65 MHz Output noise level @ minimum gain 1.3 nV/√Hz Maintains 75 Ω output impedance in TX-enable and Transmit-disable condition Upper bandwidth: 100 MHz (full gain range) 3.3 V supply operation Supports SPI® interfaces APPLICATIONS DOCSIS 2.0 and Euro-DOCSIS cable modems CATV set-top boxes CATV telephony modems Coaxial and twisted pair line drivers GENERAL DESCRIPTION The AD83241 is a low cost amplifier designed for coaxial line driving. The features and specifications make the AD8324 ideally suited for DOCSIS 2.0 and Euro-DOCSIS applications. The gain of the AD8324 is digitally controlled. An 8-bit serial word determines the desired output gain over a 59 dB range, resulting in gain changes of 1 dB/LSB. The AD8324 accepts a differential or single-ended input signal. The output is specified for driving a 75 Ω load through a 1:1 transformer. Distortion performance of –54 dBc is achieved with an output level up to 61 dBmV at 65 MHz bandwidth. This device has a sleep mode function that reduces the quies- cent current to 30 μA and a full power-down function that reduces power-down current to 2.5 mA. The AD8324 is packaged in a low cost 20-lead LFCSP package and a 20-lead QSOP package. The AD8324 operates from a single 3.3 V supply. FUNCTIONAL BLOCK DIAGRAM VIN+ VIN– VOUT+ VOUT– ZIN (SINGLE) = 550Ω ZIN (DIFF) = 1100Ω RAMP ZOUT DIFF = 75 Ω SHIFT REGISTER DATA LATCH DECODE POWER- DOWN LOGIC GND DATEN DATA CLK TXEN SLEEP 8 8 8 AD8324 VERNIER DIFF OR SINGLE INPUT AMP OUTPUT STAGE BYP ATTENUATION CORE Figure 1. Functional Block Diagram FREQUENCY (MHz) 515 –80 –70 –50 –60 –40 25 35 45 55 65 VOUT = 61dBmV @ DEC 60 SECOND HARMONIC VOUT = 61dBmV @ DEC 60 THIRD HARMONIC Figure 2. Worst Harmonic Distortion vs. Frequency 1 Patent pending. |
Ähnliche Teilenummer - AD8324_05 |
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Ähnliche Beschreibung - AD8324_05 |
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