AD8324JRQ-REEL7 datasheet(4/16 Pages) AD

Teilenummer	AD8324JRQ-REEL7

Bauteilbeschribung	3.3 V Upstream Cable Line Driver

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Hersteller	AD [Analog Devices]

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AD8324

Rev. A | Page 4 of 16

LOGIC INPUTS (TTL/CMOS COMPATIBLE LOGIC)

DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 3.3 V, unless otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

Logic 1 Voltage

2.1

3.3

V

Logic 0 Voltage

0

0.8

V

Logic 1 Current (VINH = 3.3 V), CLK, SDATA, DATEN

0

20

nA

Logic 0 Current (VINL = 0 V), CLK, SDATA, DATEN

−600

−100

nA

Logic 1 Current (VINH = 3.3 V), TXEN

50

190

μA

Logic 0 Current (VINL = 0 V), TXEN

−250

−30

μA

Logic 1 Current (VINH = 3.3 V), SLEEP

50

190

μA

Logic 0 Current (VINL = 0 V), SLEEP

−250

−30

μA

TIMING REQUIREMENTS

VCC = 3.3 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted.

Table 3.

Parameter

Min

Typ

Max

Unit

Clock Pulse Width (tWH)

16.0

ns

Clock Period (tC)

32.0

ns

Setup Time SDATA vs. Clock (tDS)

5.0

ns

Setup Time DATEN vs. Clock (tES)

15.0

ns

Hold Time SDATA vs. Clock (tDH)

5.0

ns

Hold Time DATEN vs. Clock (tEH)

3.0

ns

Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF)

10

ns

tDS

CLK

VALID DATA WORD G1

MSB . . . LSB

SDATA

DATEN

TXEN

ANALOG

OUTPUT

VALID DATA WORD G2

8 CLOCK CYCLES

GAIN TRANSFER (G1)

GAIN TRANSFER (G2)

SIGNAL AMPLITUDE (p-p)

tC

tVUH

tES

tEH

tOFF

tGS

tCN

Figure 3. Serial Interface Timing

CLK

SDATA

MSB

MSB-1

MSB-2

VALID DATA BIT

tDS

tDH

Figure 4. SDATA Timng

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