Datenblatt-Suchmaschine für elektronische Bauteile |
|
CS82C50A-5Z Datenblatt(PDF) 11 Page - Intersil Corporation |
|
CS82C50A-5Z Datenblatt(HTML) 11 Page - Intersil Corporation |
11 / 25 page 11 FN2958.5 August 24, 2006 82C50A MSR(3) Delta Data Carrier Detect (DDCD): DDCD indicates that the DCD input (Pin-36) to the 82C50A has changed state since the last time it was read by the CPU. MSR(4) Clear to Send (CTS): Clear to Send (CTS) is the status of the CTS input (Pin-36) from the modem indicating to the 82C50A that the modem is ready to receive data from the 62C50A transmitter output (SOUT). If the 82C50A is in the loop mode (MCR(4)=1), MSR(4) is equivalent to RTS in the MCR. MSR(5) Data Set Ready (DSR): Data Set Ready (DSR) is a status of the DSR input (Pin-37) from the modem to the 82C50A which indicates that the modem is ready to provide received data to the 82C50A receiver circuitry. If the 82C50A is in the loop mode (MCR(4) = 1), MSR(5) is equivalent to DTR in the MCR. MSR(6) Ring Indicator MSR(6): Indicates the status of the RI input (Pin-39). If the 82C50A is in the loop mode (MCR(4) = 1), MSR(6) is equivalent to OUT1 in the MCR. MSR(7) Data Carrier Detect (MSR(7)): Data Carrier Detect indicates the status of the Data Carrier Detect (DCD) input (Pin-38). If the 82C50A is in the loop mode (MCR(4) = 1), MSR(4) is equivalent to OUT2 of the MCR. The modem status inputs (RI, DCD, DSR and CTS) reflect the modem input lines with any change of status. Reading the MSR register will clear the delta modem status indications but has no effect on the status bits. The status bits reflect the state of the input pins regardless of the mask control signals. If a DCTS, DDSR, TERI, or DDCD are true and a state change occurs during a read operation (DlSTR, DISTR), the state change is not indicated in the MSR. If DCTS, DDSR, TERI, or DDCD are false and a state change occurs during a read operation, the state change is indicated after the read operation. For LSR and MSR, the setting of status bits is inhibited during status register read (DISTR, DlSTR) operations. If a status condition is generated during a read (DlSTR, DISTR) operation, the status bit is not set until the trailing edge of the read (DISTR, DISTR). If a status bit is set during a read (DlSTR, DISTR) operation, and the same status condition occurs, that status bit will be cleared at the trailing edge of the read (DlSTR, DISTR) instead of being set again. BAUD RATE SELECT REGISTER (BRSR) The 82C50A contains a programmable Baud Rate Generator (BRG) that divides the clock (DC to 10MHz) by any divisor from 1 to 216-1 (see also BRG description). The output frequency of the Baud Generator is 16X the data rate [divisor # = frequency input ÷ (baud rate x 16)]. Two 8-bit divisor latch registers store the divisor in a 16-bit binary format. These Divisor Latch registers must be loaded during initialization. Upon loading either of the Divisor Latches, a 16-bit Baud counter is immediately loaded. This prevents long counts on initial load. Sample Divisor Number Calculation: Given: Desired Baud Rate 1200 Baud Frequency Input 1.8432MHz Formula: Divisor # = Frequency Input ÷ (Baud Rate x 16) Divisor # = 1843200 ÷ (1200 x 16) Answer: Divisor # = 96 = 60HEX → DLL = 01100000 DLM = 00000000 Check: The Divisor # 96 will divide the input frequency 1.8432MHz down to 19200 which is 16 times the desired baud rate. RECEIVER BUFFER REGISTER (RBR) The receiver circuitry in the 82C50A is programmable for 5, 6, 7 or 8 data bits per character. For words of less than 8 bits, the data is right justified to the least significant bit (LSB = Data Bit 0 (RBR(0)). Data Bit 0 of a data word (RBR(0)) is the first data bit received. The unused bits in a character less than 8 bits are output low to the parallel output by the 82C50A. Received data at the SIN input pin is shifted into the Receiver Shift Register by the 16X clock provided at the RCLK input. This clock is synchronized to the incoming data based on the position of the start bit. When a complete character is shifted into the Receiver Shift Register, the assembled data bits are parallel loaded into the Receiver Buffer Register. The DR flag in the LSR register is set. Double buffering of the received data permits continuous reception of data without losing received data. While the Receiver Shift Register is shifting a new character into the 82C50A, the Receiver Buffer Register is holding a previously received character for the CPU to read. Failure to read the Divisor Latch Least Significant BYTE DLL (0) Bit 0 DLL (1) Bit 1 DLL (2) Bit 2 DLL (3) Bit 3 DLL (4) Bit 4 DLL (5) Bit 5 DLL (6) Bit 6 DLL (7) Bit 7 Divisor Latch Most Significant BYTE DLM (0) Bit 8 DLM (1) Bit 9 DLM (2) Bit 10 DLM (3) Bit 11 DLM (4) Bit 12 DLM (5) Bit 13 DLM (6) Bit 14 DLM (7) Bit 15 |
Ähnliche Teilenummer - CS82C50A-5Z |
|
Ähnliche Beschreibung - CS82C50A-5Z |
|
|
Link URL |
Privatsphäre und Datenschutz |
ALLDATASHEETDE.COM |
War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |