CS82C37A datasheet(7/24 Pages) INTERSIL

Teilenummer	CS82C37A

Bauteilbeschribung	CMOS High Performance Programmable DMA Controller

Download	24 Pages

Scroll/Zoom	100%

Hersteller	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

Logo

7 / 24 page

7

FN2967.2

March 20, 2006

82C37A

After the I/O device has had a chance to catch up, the DMA

service is reestablished by means of a DREQ. During the time

between services when the microprocessor is allowed to

operate, the intermediate values of address and word count are

stored in the 82C37A Current Address and Current Word Count

registers. Higher priority channels may intervene in the demand

process, once DREQ has gone inactive. Only an EOP can

cause an Autoinitialization at the end of service. EOP is

generated either by TC or by an external signal.

Cascade Mode - This mode is used to cascade more than

one 82C37A for simple system expansion. The HRQ and

HLDA signals from the additional 82C37A are connected to

the DREQ and DACK signals respectively of a channel for

the initial 82C37A.This allows the DMA requests of the

additional device to propagate through the priority network

circuitry of the preceding device. The priority chain is

preserved and the new device must wait for its turn to

acknowledge requests. Since the cascade channel of the

initial 82C37A is used only for prioritizing the additional

device, it does not output an address or control signals of its

own. These could conflict with the outputs of the active

channel in the added device. The initial 82C37A will respond

to DREQ and generate DACK but all other outputs except

HRQ will be disabled. An external EOP will be ignored by the

initial device, but will have the usual effect on the added

device.

Figure 3 shows two additional devices cascaded with an

initial device using two of the initial device’s channels. This

forms a two-level DMA system. More 82C37As could be

added at the second level by using the remaining channels

of the first level. Additional devices can also be added by

cascading into the channels of the second level devices,

forming a third level.

When programming cascaded controllers, start with the first

level device (closest to the microprocessor). After RESET,

the DACK outputs are programmed to be active low and are

held in the high state. If they are used to drive HLDA directly,

the second level device(s) cannot be programmed until

DACK polarity is selected as active high on the initial device.

Also, the initial device’s mask bits function normally on

cascaded channels, so they may be used to inhibit second-

level services.

Transfer Types

Each of the three active transfer modes can perform three

different types of transfers. These are Read, Write and Verify.

Write transfers move data from an I/O device to the memory

by activating MEMW and IOR. Read transfers move data from

memory to an I/O device by activating MEMR and IOW.

Verify transfers are pseudo-transfers. The 82C37A operates

as in Read or Write transfers generating addresses and

responding to EOP, etc., however the memory and I/O

control lines all remain inactive. Verify mode is not permitted

for memory-to-memory operation. READY is ignored during

Verify transfers.

Autoinitialize - By setting bit 4 in the Mode register, a

channel may be set up as an Autoinitialize channel. During

Autoinitialization, the original values of the Current Address

and Current Word Count registers are automatically restored

from the Base Address and Base Word Count registers of

the channel following EOP. The base registers are loaded

simultaneously with the current registers by the

microprocessor and remain unchanged throughout the DMA

service. The mask bit is not set when the channel is in

Autoinitialize mode. Following Autoinitialization, the channel

is ready to perform another DMA service, without CPU

intervention, as soon as a valid DREQ is detected, or

software request made.

Memory-to-Memory - To perform block moves of data from

one memory address space to another with minimum of

program effort and time, the 82C37A includes a memory-to-

memory transfer feature. Setting bit 0 in the Command

register selects channels 0 and 1 to operate as memory-to-

memory transfer channels.

The transfer is initiated by setting the software or hardware

DREQ for channel 0. The 82C37A requests a DMA service

in the normal manner. After HLDA is true, the device, using

four-state transfers in Block Transfer mode, reads data from

the memory. The channel 0 Current Address register is the

source for the address used and is decremented or

incremented in the normal manner. The data byte read from

the memory is stored in the 82C37A internal Temporary

register. Another four-state transfer moves the data to

memory using the address in channel one’s Current Address

register and incrementing or decrementing it in the normal

manner. The channel 1 Current Word Count is decremented.

When the word count of channel 1 decrements to FFFFH, a

TC is generated causing an EOP output, terminating the

service, and setting the channel 1 TC bit in the Status

register. The channel 1 mask bit will also be set, unless the

channel 1 mode register is programmed for autoinitialization.

80C86/88

MICRO-

PROCESSOR

HRQ

HLDA

DREQ

DACK

DREQ

DACK

1ST LEVEL

82C37A

HRQ

HLDA

82C37A

HRQ

HLDA

82C37A

ADDITIONAL

DEVICES

2ND LEVEL

INITIAL DEVICE

FIGURE 3. CASCADED 82C37As

CS82C37A Datenblatt(PDF) 7 Page - Intersil Corporation

CS82C37A Datenblatt(HTML) 7 Page - Intersil Corporation

Ähnliche Teilenummer - CS82C37A

Ähnliche Beschreibung - CS82C37A

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datenblatt Download

Link URL