AM42BDS6408HD3I datasheet(7/90 Pages) SPANSION

Teilenummer	AM42BDS6408HD3I

Bauteilbeschribung	CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory, and 8 Mbit (512 K x 16-Bit) SRAM

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October 23, 2003

Am42BDS6408H

5

A D VA NCE

I N FO RM ATIO N

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 48

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 49

CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . 49

SRAM DC and Operating Characteristics . . . . . . 50

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 10. Test Setup............................................................................ 51

Table 19. Test Specifications ................................................................51

Key to Switching Waveforms . . . . . . . . . . . . . . . 51

Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 51

Figure 11. Input Waveforms and Measurement Levels ........................ 51

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 52

VCC Power-up ..............................................................................52

Figure 12. VCC Power-up Diagram ....................................................... 52

Synchronous/Burst Read (VIO = 1.8 V) ........................................53

Figure 13. CLK Synchronous Burst Mode Read (rising active CLK)..... 54

Figure 14. CLK Synchronous Burst Mode Read (Falling Active Clock) 54

Figure 15. Synchronous Burst Mode Read ........................................... 55

Figure 16. 8-word Linear Burst with Wrap Around ................................ 55

Figure 17. Linear Burst with RDY Set One Cycle Before Data ............. 56

Figure 18. Reduced Wait-state Handshake Burst Suspend/Resume at an

even address......................................................................................... 57

Figure 19. Reduced Wait-state Handshake Burst Suspend/Resume at an

odd address .......................................................................................... 57

Figure 20. Reduced Wait-state Handshake Burst Suspend/Resume at ad-

dress 3Eh (or offset from 3Eh) .............................................................. 58

Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume at ad-

dress 3Fh (or offset from 3Fh by a multiple of 64) ................................ 58

Figure 22. Standard Handshake Burst Suspend prior to Initial Access 59

Figure 23. Standard Handshake Burst Suspend at or after Inital Access ..

59

Figure 24. Standard Handshake Burst Suspend at address 3Fh (starting

address 3Dh or earlier) ......................................................................... 60

Figure 25. Standard Handshake Burst Suspend at address 3Eh/3Fh (with-

out a valid Initial Access)....................................................................... 60

Figure 26. Standard Handshake Burst Suspend at address 3Eh/3Fh (with

1 Access CLK) ...................................................................................... 61

Figure 27. Read Cycle for Continuous Suspend................................... 61

Asynchronous Mode Read (VIO = 1.8 V) ......................................62

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 28. Asynchronous Mode Read with Latched Addresses ........... 63

Figure 29. Asynchronous Mode Read................................................... 63

Figure 30. Reset Timings...................................................................... 64

Erase/Program Operations (VIO = 1.8 V) ..................................... 65

Figure 31. Asynchronous Program Operation Timings: AVD# Latched Ad-

dresses ................................................................................................. 66

Figure 32. Asynchronous Program Operation Timings: WE# Latched Ad-

dresses ................................................................................................. 67

Figure 33. Synchronous Program Operation Timings: WE# Latched Ad-

dresses ................................................................................................. 68

Figure 34. Synchronous Program Operation Timings: CLK Latched Ad-

dresses ................................................................................................. 69

Figure 35. Chip/Sector Erase Command Sequence............................. 70

Figure 36. Accelerated Unlock Bypass Programming Timing .............. 71

Figure 37. Data# Polling Timings (During Embedded Algorithm) ......... 72

Figure 38. Toggle Bit Timings (During Embedded Algorithm) .............. 72

Figure 39. Synchronous Data Polling Timings/Toggle Bit Timings....... 73

Figure 40. DQ2 vs. DQ6 ....................................................................... 73

Temporary Sector Unprotect ........................................................ 74

Figure 41. Temporary Sector Unprotect Timing Diagram ..................... 74

Figure 42. Sector/Sector Block Protect and

Unprotect Timing Diagram.................................................................... 75

Figure 43. Latency with Boundary Crossing ......................................... 76

Figure 44. Latency with Boundary Crossing

into Program/Erase Bank...................................................................... 77

Figure 45. Example of Wait States Insertion ........................................ 78

Figure 46. Back-to-Back Read/Write Cycle Timings............................. 79

SRAM AC Characteristics . . . . . . . . . . . . . . . . . . 80

Read Cycle ................................................................................... 80

Figure 47. SRAM Read Cycle—Address Controlled ............................ 80

Figure 48. SRAM Read Cycle............................................................... 81

Write Cycle ................................................................................... 82

Figure 49. SRAM Write Cycle—WE# Control....................................... 82

Figure 50. SRAM Write Cycle—CE1#s Control.................................... 83

Figure 51. SRAM Write Cycle—UB#s and LB#s Control...................... 84

Erase and Programming Performance . . . . . . . 85

BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 85

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 86

TLB 089—89-ball Fine-Pitch Ball Grid Array (FBGA) 10 x

8 mm Package ............................................................................. 86

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 87

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