Datenblatt-Suchmaschine für elektronische Bauteile |
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AM49PDL129AH61IT Datenblatt(PDF) 8 Page - SPANSION |
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AM49PDL129AH61IT Datenblatt(HTML) 8 Page - SPANSION |
8 / 82 page 6 Am49PDL127AH/Am49PDL129AH December 18, 2003 ADV ANCE I N FO RMAT I O N Between Pseudo SRAM and Flash................................................. 59 Flash AC Characteristics . . . . . . . . . . . . . . . . . . . 60 Read-Only Operations – Am29PDL127H ............................... 60 Read-Only Operations – Am29PDL129H ............................... 60 Figure 13. Read Operation Timings ................................................ 61 Figure 14. Page Read Operation Timings....................................... 61 Hardware Reset (RESET#) .................................................... 62 Figure 15. Reset Timings ................................................................ 62 Erase and Program Operations .............................................. 63 Figure 16. Program Operation Timings........................................... 64 Figure 17. Accelerated Program Timing Diagram........................... 64 Figure 18. Chip/Sector Erase Operation Timings ........................... 65 Figure 19. Back-to-back Read/Write Cycle Timings ....................... 66 Figure 20. Data# Polling Timings (During Embedded Algorithms).. 66 Figure 21. Toggle Bit Timings (During Embedded Algorithms)....... 67 Figure 22. DQ2 vs. DQ6.................................................................. 67 Temporary Sector Unprotect .................................................. 68 Figure 23. Temporary Sector Unprotect Timing Diagram ............... 68 Figure 24. Sector/Sector Block Protect and Unprotect Timing Diagram .............................................................. 69 Alternate CE#f1 Controlled Erase and Program Operations .. 70 Figure 25. Flash Alternate CE#f1 Controlled Write (Erase/Program) Operation Timings.......................................................................... 71 Pseudo SRAM AC Characteristics . . . . . . . . . . . 72 Power Up Time ....................................................................... 72 Read Cycle ............................................................................. 72 Figure 26. Pseudo SRAM Read Cycle—Address Controlled......... 72 Figure 27. Pseudo SRAM Read Cycle........................................... 73 Write Cycle ............................................................................. 74 Figure 28. Pseudo SRAM Write Cycle—WE# Control ................... 74 Figure 29. Pseudo SRAM Write Cycle—CE1#s Control ................ 75 Figure 30. Pseudo SRAM Write Cycle— UB#s and LB#s Control.................................................................. 76 Erase And Programming Performance . . . . . . . 77 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 77 Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 77 Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 77 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 78 TLA073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 78 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 79 |
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