©1990 Fairchild Semiconductor Corporation

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74ACQ573, 74ACTQ573 Rev. 1.5

2

Logic Symbol

IEEE/IEC

Functional Description

The ACQ/ACTQ573 contains eight D-type latches with

3-STATE output buffers. When the Latch Enable (LE)

In this condition the latches are transparent, i.e., a latch

output will change state each time its D-type input

changes. When LE is LOW the latches store the informa-

tion that was present on the D-type inputs at setup time

preceding the HIGH-to-LOW transition of LE. The

3-STATE buffers are controlled by the Output Enable

(OE) input. When OE is LOW, the buffers are enabled.

When OE is HIGH the buffers are in the high impedance

mode but this does not interfere with entering new data

into the latches.

Truth Table

H

= HIGH Voltage

L

= LOW Voltage

Z

= High Impedance

X

= Immaterial

Latch Enable

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

Inputs

Outputs

OE

LE

D

LH

H

H

LH

L

L

LL

X

HX

X

Z