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GROUNDING

SIGNAL CONDITIONING

INTERMEDIATE LATCHES

ADS8507

SLAS381 – DECEMBER 2006

LAYOUT (continued)

from the digital logic. For best performance, the +5-V supply can be produced from whatever analog supply is

used for the rest of the analog signal conditioning. If +12-V or +15-V supplies are present, a simple +5-V

regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be

Three ground pins are present on the ADS8507. DGND is the digital supply ground. AGND2 is the analog

supply ground. AGND1 is the ground to which all analog signals internal to the A/D converter are referenced.

AGND1 is more susceptible to current induced voltage drops and must have the path of least resistance back to

the power supply.

All the ground pins of the A/D converter should be tied to an analog ground plane, separated from the system's

digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to

the system ground as near to the power supplies as possible. This helps to prevent dynamic digital ground

currents from modulating the analog ground through a common impedance to power ground.

The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of

charge injection which can cause the driving op amp to oscillate. The amount of charge injection due to the

sampling FET switch on the ADS8507 is approximately 5% to 10% of the amount on similar A/D converters with

the charge redistribution digital-to-analog converter (DAC) CDAC architecture. There is also a resistive front end

which attenuates any charge which is released. The end result is a minimal requirement for the drive capability

on the signal conditioning preceding the A/D converter. Any op amp sufficient for the signal in an application will

be sufficient to drive the ADS8507.

The resistive front end of the ADS8507 also provides a specified ±25-V overvoltage protection. In most cases,

this eliminates the need for external over-voltage protection circuitry.

The ADS8507 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus

is active during conversions. If the bus is not active during conversion, the 3-state outputs can be used to isolate

the A/D converter from other peripherals on the same bus.

Intermediate latches are beneficial on any monolithic A/D converter. The ADS8507 has an internal LSB size of

38 µV. Transients from fast switching signals on the parallel port, even when the A/D converter is 3-stated, can

be coupled through the substrate to the analog circuitry causing degradation of converter performance.

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