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TPS60250 Datenblatt(Datasheet) 3 Page - Texas Instruments

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Teile-Nr. TPS60250
Beschreibung  HIGH EFFICIENCY CHARGE PUMP FOR 7 WLEDs WITH I2C INTERFACE
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Hersteller  TI [Texas Instruments]
Homepage  http://www.ti.com
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TPS60250
SLVS769 – APRIL 2007
ELECTRICAL CHARACTERISTICS (continued)
V
I = 3.5 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Vhys
Under-voltage lockout hysterisis
UVLO1
210
mV
VI = 3 V, CO = 1 µF,
TS
Soft start time(3)
0.5
ms
IMAIN_LED = 15 mA × 4
CHARGE PUMP
Vout
Overvoltage limit
6.5
V
Fs
Switching frequency
750
kHz
×1 Mode, (V
I– VO)/IO
1.2
RO
Open loop output impedance
× 1.5 Mode, (V
I× 1.5 – VO)/IO VI = 3.0V (IO =
3.5
5.0
120mA)
CURRENT SINK
Current matching of sub LEDs at light
ISUB_LED = 100 µA × 2, VDXX = 0.4 V
Km_sub
0
±2%
load condition(4)
IMAIN_LED = 15 mA × 4,
Km_main
LED to LED Current matching(5)
±1%
±5%
3.0 V
≤ V
I ≤ 4.2 V
Ka
Current accuracy
ILED = 15 mA
±7%
Main and Sub Display Current Register =
Maximum LED current of DM1-4 and
ID_MS
0
×01&2(111111),
25.5
mA
DS1-2
VDXX = 0.2 V
Aux Display Current Register = 0
×03
ID_DM5
Maximum LED current of DM5
80
mA
(XXXX11), VDM5 = 0.4 V
VDropOut
LED Drop out voltage
See (6)
80
120
mV
1
× Mode to 1.5× mode transition
VDXX Falling, 15 mA × 4 measured on the
VTH_GU
85
100
120
mV
threshold voltage(7)
lowest VDXX
Input voltage hysteresis for 1.5
× to 1×
Measured as VI– (VO– VDXX_MIN), IMAIN_LED = 15
VTH_GD
470
mV
mode transition
mA
× 4
SERIAL INTERFACE TIMING REQUIREMENTS
fmax
Clock frequency
400
kHz
twH(HIGH)
Pulse duration, clock high time
600
ns
twL(LOW)
Pulse duration, clock low time
1300
ns
tr
DATA and CLK rise time
300
ns
tf
DATA and CLK fall time
300
ns
High time (repeated) START
th(STA)
condition(after this period the first clock
600
ns
pulse is generated)
Setup time for repeated START
tsu(STA)
600
ns
condition
th(DATA)
Data input hold time
0
ns
tsu(DATA)
Data input setup time
100
ns
tsu(STO)
STOP condition setup time
600
ns
t(BUF)
Bus free time
1300
ns
I2C COMPATIBLE INTERFACE VOLTAGE SPECIFICATION (SCLK, SDAT, VIO)
VIL
Low-leveI input voltage
3.0V
≤ V
I ≤ 6.0V
0
0.5
V
VIH
High-level input voltage
3.0V
≤ V
I ≤ 6.0V
1.1
V
VOL
Low-level output voltage
ILOAD = 2 mA
0.4
V
(3)
Measurement Condition: From enabling the LED driver to 90% output voltage after VI is already up.
(4)
LED current matching is defined as: (ISUB_LED_WORST – IAVG_SUB) / IAVG_SUB
(5)
LED to LED Current Matching is defined as: (IMAIN_LED_WORST – IAVG_MAIN) / IAVG_MAIN
(6)
Dropout Voltage is defined as VDXX (WLED Cathode) to GND voltage at which current into the LED drops 10% from the LED current at
VDXX = 0.2 V, WLED current = 15 mA × 4.
(7)
As VI drops, VDXX eventually falls below the switchover threshold of 100mV, and TPS60250 switches to 1.5× mode. See the Operating
Principle section for details about the mode transition thresholds.
3
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