Datenblatt-Suchmaschine für elektronische Bauteile |
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74VHC240MTC Datenblatt(PDF) 1 Page - Fairchild Semiconductor |
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74VHC240MTC Datenblatt(HTML) 1 Page - Fairchild Semiconductor |
1 / 9 page tm April 2007 ©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC240 Rev. 1.3 74VHC240 Octal Buffer/Line Driver with 3-STATE Outputs Features ■ High Speed: tPD = 3.6ns (typ) at TA = 25°C ■ Low power dissipation: ICC = 4µA (max) @ TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min.) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.9V (max.) ■ Pin and function compatible with 74HC240 General Description The VHC240 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC240 is an inverting 3-STATE buffer having two active-LOW output enables. This device is designed to drive buslines or buffer memory address registers. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Descriptions Order Number Package Number Package Description 74VHC240M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74VHC240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Description OE1, OE2 3-STATE Output Enable Inputs I0–I7 Inputs O0–O7 Outputs 3-STATE Outputs |
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Ähnliche Beschreibung - 74VHC240MTC |
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