AD5522JSVUZ datasheet(7/48 Pages) AD

Teilenummer	AD5522JSVUZ

Bauteilbeschribung	Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs

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Preliminary Technical Data

AD5522

Rev. PrM | Page 7 of 48

DAC SPECIFICATIONS

Resolution

16

Bits

Voltage Output Span2

22.5

V

VREF=5V, within a range of -16.25 to 22.5V

Differential Nonlinearity2

-1

1

LSB

Guaranteed monotonic by design over temperature.

COMPARATOR DAC DYNAMIC

SPECIFICATIONS

Output Voltage Settling Time2

1.5

µs

500mV change to ±½ LSB.

Slew Rate2

5.5

V/µs

Digital-to-Analog Glitch Energy2

20

nV-s

Glitch Impulse Peak Amplitude2

10

mV

REFERENCE INPUT

VREF DC Input Impedance

1

MΩ

Typically 100 MΩ.

VREF Input Current

-10

10

µA

Per input. Typically ±30 nA.

VREF Range

2

5

V

DIE TEMPERATURE SENSOR

Accuracy

±7

°C

Output Voltage at 25°C

1.5

V

Output Scale Factor

5

mV/°C

Output Voltage Range

0

3

V

INTERACTION & CROSSTALK

Crosstalk (VM)2

-0.01

0.01

% FSR

All channels in FIMV mode, measure the voltage for one

channel in the highest current force range, once when all

three other channels are at FI = 0mA and once when

they are at 2mA

Crosstalk (MI)2

-0.01

0.01

% FSR

All channels in FVMI mode, measure the current for one

channel in the lowest current measure range, once when

all three other channels are at FV = -10V and once when

they are at +10V

Crosstalk within a channel2

0.5

mV

All channels in FVMI mode, one channel at midscale,

measure the current for one channel in the lowest

current range, for a change in comparator or clamp DAC

levels for that PMU.

Shorted DUT Crosstalk2

TBD

S/C applied to one PMU channel, measure effect on

other channels.

SPI INTERFACE LOGIC

LOGIC INPUTS

VIH, Input High Voltage

1.7/2.0

V

(2.3 to 2.7)/(2.7 to 5.25V) Jedec Compliant Input Levels

VIL, Input Low Voltage

0.7/0.8

V

(2.3 to 2.7)/(2.7 to 5.25V) Jedec Compliant Input Levels

IINH, IINL, Input Current

-1

1

µA

CIN, Input Capacitance2

10

pF

CMOS LOGIC OUTPUTS

SDO, CPOX

VOH, Output High Voltage

DVCC – 0.4

V

VOL, Output Low Voltage

0.4

V

IOL = 500 µA

Tristate leakage current

-1

1

µA

Output Capacitance2

10

pF

OPEN DRAIN LOGIC OUTPUTS

BUSY, TMPALM, CGALM

VOL, Output Low Voltage

0.4

V

IOL = 500 µA, CL = 50pF, RPULLUP = 1kΩ

Output Capacitance2

10

pF

LVDS INTERFACE LOGIC

LOGIC INPUTS – Reduced Range Link

Input Voltage Range

875

1575

mV

Input Differential Threshold

-100

100

mV

External Termination Resistance

80

100

120

Ω

Differential Input Voltage

100

mV

LOGIC OUTPUTS – Reduced Range Link

Output Offset Voltage

1200

mV

Output Differential Voltage

400

mV

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