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TMP470R1B512PGE Datenblatt(PDF) 10 Page - Analog Devices |
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TMP470R1B512PGE Datenblatt(HTML) 10 Page - Analog Devices |
10 / 49 page www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 Table 2. Terminal Functions (continued) TERMINAL INTERNAL TYPE(1)(2) PULLUP/ DESCRIPTION NAME NO. PULLDOWN(3) SYSTEM MODULE (SYS) Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output CLKOUT 83 3.3-V I/O IPD (20 µA) of SYSCLK, ICLK, or MCLK. Input master chip power-up reset. External VCC monitor circuitry must PORRST 32 3.3-V I IPD (20 µA) assert a power-on reset. Bidirectional reset. The internal circuitry can assert a reset, and an external system reset can assert a device reset. On this pin, the output buffer is implemented as an open drain (drives low RST 15 3.3-V I/O IPU (20 µA) only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor be connected to this pin. WATCHDOG/REAL-TIME INTERRUPT (WD/RTI) Analog watchdog reset. The AWD pin provides a system reset if the WD KEY is not written in time by the system, providing an external RC network circuit is connected. AWD 72 3.3-V I/O IPD (20 µA) If the user is not using AWD, TI recommends that this pin be connected to ground or pulled down to ground by an external resistor. For more details on the external RC network circuit, see the TMS470R1x System Module Reference Guide (literature number SPNU189). TEST/DEBUG (T/D) TCK 76 3.3-V I IPD (20 µA) Test clock. TCK controls the test hardware (JTAG). Test data in. TDI inputs serial data to the test instruction register, test data TDI 74 3.3-V I IPU (20 µA) register, and programmable test address (JTAG). Test data out. TDO outputs serial data from the test instruction register, TDO 75 3.3-V O IPD (20 µA) test data register, identification register, and programmable test address (JTAG). Test enable. Reserved for internal use only. TI recommends that this pin TEST 38 3.3-V I IPD (20 µA) be connected to ground or pulled down to ground by an external resistor. Serial input for controlling the state of the CPU test access port (TAP) TMS 120 3.3-V I IPU (20 µA) controller (JTAG) Serial input for controlling the second TAP. TI recommends that this pin be TMS2 121 3.3-V I IPU (20 µA) connected to VCCIO or pulled up to VCCIO by an external resistor. Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG) TRST 37 3.3-V I IPD (20 µA) Boundary-Scan Logic. TI recommends that this pin be pulled down to ground by an external resistor. FLASH Flash test pad 1. For proper operation, this pin must not be connected FLTP1 134 NC [no connect (NC)]. Flash test pad 2. For proper operation, this pin must not be connected FLTP2 133 NC [no connect (NC)]. Flash external pump voltage (3.3 V). This pin is required for both flash VCCP 135 3.3-V PWR read and flash program and erase operations. SUPPLY VOLTAGE CORE (1.8 V) 14 31 55 VCC 86 1.8-V PWR Core logic supply voltage 93 128 132 10 Submit Documentation Feedback |
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