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TDA4821P Datenblatt(PDF) 7 Page - NXP Semiconductors |
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TDA4821P Datenblatt(HTML) 7 Page - NXP Semiconductors |
7 / 20 page 2000 Feb 09 7 Philips Semiconductors Product specification Autosize IC for colour monitors TDA4821P Table 1 Vertical timing measurements TIMING BITS CONDITIONS VsWidth 8 trailing edge of pulse on pin VS VfstVid 12 first line with active video on pins VIN1, VIN2 or VIN3 VlstVid 12 last line with active video on pins VIN1, VIN2 or VIN3 Vperiod 12 next leading edge of pulse on pin VS handbook, full pagewidth MHB653 VlstVid Vperiod VsWidth VfstVid vertical sync (pin VS) R, G, B video inputs (pins VIN1, VIN2, VIN3) horizontal sync Fig.3 Vertical timing. HORIZONTAL TIMING MEASUREMENTS The parameters are measured with respect to the leading edge of the H-sync pulses (see Fig.4). At the leading edge of the H-sync pulse on pin HS a 12-bit clock counter is started (nominal internal clock frequency is 48 MHz). The six horizontal timings (see Table 2) are countered as a number of internal clock pulses and stored in buffer registers. The contents of these buffer registers are copied to the I2C-bus data registers on every next leading edge of the V-sync pulse with the addition of LSBs (logic 0) for completing the full 2-byte data. The measurements of HsWidth, Hperiod, Hfbstrt and Hfbstop in line 64 prevent wrong data capturing caused by post-equalizing sync pulses. The minimum horizontal frequency is 12 kHz and Hperiod displays the full 12 bits. At 125 kHz, the shorter Hperiod will display 9 bits only but the resolution is still better than 0.25%. |
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