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TDA5360UK Datenblatt(PDF) 5 Page - NXP Semiconductors |
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TDA5360UK Datenblatt(HTML) 5 Page - NXP Semiconductors |
5 / 34 page 1998 July 30 Philips Semiconductors Objective Specification, Revision 2.2 Pre-Amplifier for Hard Disk Drive with MR-Read / Inductive Write Heads TDA5360 5 4 DESCRIPTION The +/- 5.0 volt pre-amplifier for HDD described here has been designed for 12 terminals, comprised of a SAL or GMR magneto-resistive reader and an inductive thin film writer. In read mode, the device operates as a low noise differential preamplifier which senses resistance changes in the MR element that correspond to flux changes on the disk. In write mode, the circuit operates as a thin film head current switch, driving the inductive element of the head. The IC incorporates Read amplifiers with programmable gain and HF boosts, Write amplifiers, 3-wires Serial Interface, Digital-to-Analog Converters, Thermal Asperity Detector and Programmable Thermal Asperity Compressor, reference and control circuits which operate on a Dual Supply Voltage of +/-5V (+/-10%). The Read amplifier has programmable medium input impedance. The DC offset between the two terminals of the MR head is eliminated using on chip AC coupling. The bandwidth can be enhanced by using programmable high frequency gain-boost. Fast settling features are used to keep the transients short. As an option, the Read amplifier may be left biased during writing, so as to reduce the duration of these transients even further. The Write amplifier has a programmable current overshoot which may be added to the programmable steady state write current. Fault protection is provided for a variety of read or write unsafe conditions. For added data protection, internal pull up resistors are connected to RWN, CS0, CS1, STWN, WDP and WDN pins and pull down resistors are connected to SEN, SDATA, SCLK, DRN and BFAST pins, to prevent accidental writing due to open lines and to ensure the device will power up in a non-writing condition. On-chip Digital to Analog converters for MR bias current or power and Write current are programmed via a 3 wire Serial Interface. Head selection, Mode control, Testing and Servo Writing can also be programmed using the serial interface. In Sleep mode, the CMOS serial interface is operationnal. Fig 2 shows the block diagram of the IC. Invalid head select codes disable the writer, select the dummy head and trigger the FLT output. 5 ORDERING INFORMATION Fig.1 Type Number EXTENDED TYPE NUMBER PACKAGE TDA5360UH bare die TDA5360UK bumped die |
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