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TMP102AIDRLT Datenblatt(PDF) 9 Page - Burr-Brown (TI) |
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TMP102AIDRLT Datenblatt(HTML) 9 Page - Burr-Brown (TI) |
9 / 19 page www.ti.com CONVERTER RESOLUTION (R1/R0) ONE-SHOT/CONVERSION READY (OS) HIGH- AND LOW-LIMIT REGISTERS BUS OVERVIEW TMP102 SBOS397 – AUGUST 2007 Both operational modes are represented in Figure 10. Table 10 and Table 11 describe the R1/R0 are read-only bits. The TMP102 converter format for the THIGH and TLOW registers. Note that the resolution is set on start up to '11'. This sets the most significant byte is sent first, followed by the temperature register to a 12 bit-resolution. least significant byte. Power-up reset values for THIGH and TLOW are: THIGH = +80°C and TLOW = +75 °C. The format of the data for T HIGH and TLOW is the same as for the Temperature Register. The TMP102 features a One-Shot Temperature Measurement mode. When the device is in Table 10. Bytes 1 and 2 of THIGH Register (1) Shutdown mode, writing a ‘1’ to the OS bit starts a single temperature conversion. During the BYTE D7 D6 D5 D4 D3 D2 D1 D0 conversion, the OS bit reads '0'. The device returns H11 H10 H9 H8 H7 H6 H5 H4 1 to the shutdown state at the completion of the single (H12) (H11) (H10) (H9) (H8) (H7) (H6) (H5) conversion. After the conversion, the OS bit reads '1'. BYTE D7 D6 D5 D4 D3 D2 D1 D0 This feature is useful for reducing power H3 H2 H1 H0 0 0 0 0 consumption in the TMP102 when continuous 2 temperature monitoring is not required. (H4) (H3) (H2) (H1) (H0) (0) (0) (0) (1) Extended mode 13-bit configuration shown in parenthesis. As a result of the short conversion time, the TMP102 can achive a higher conversion rate. A single Table 11. Bytes 1 and 2 of TLOW Register (1) conversion typically takes 26ms and a read can take place in less than 20 μs. When using One-Shot BYTE D7 D6 D5 D4 D3 D2 D1 D0 mode, 30 or more conversions per second are L11 L10 L9 L8 L7 L6 L5 L4 1 possible. (L12) (L11) (L10) (L9) (L8) (L7) (L6) (L5) BYTE D7 D6 D5 D4 D3 D2 D1 D0 L3 L2 L1 L0 0 0 0 0 In Comparator mode (TM = 0), the ALERT pin 2 (L4) (L3) (L2) (L1) (L0) (0) (0) (0) becomes active when the temperature equals or (1) Extended mode 13-bit configuration shown in parenthesis. exceeds the value in THIGH and generates a consecutive number of faults according to fault bits F1 and F0. The ALERT pin remains active until the temperature falls below the indicated TLOW value for The device that initiates the transfer is called a the same number of faults. master, and the devices controlled by the master are In Interrupt mode (TM = 1), the ALERT pin becomes slaves. The bus must be controlled by a master active when the temperature equals or exceeds the device that generates the serial clock (SCL), controls value in THIGH for a consecutive number of fault the bus access, and generates the START and conditions (as shown in Table 9). The ALERT pin STOP conditions. remains active until a read operation of any register To address a specific device, a START condition is occurs, or the device successfully responds to the initiated, indicated by pulling the data-line (SDA) from SMBus Alert Response address. The ALERT pin will a high to low logic level while SCL is high. All slaves also be cleared if the device is placed in Shutdown on the bus shift in the slave address byte on the mode. Once the ALERT pin is cleared, it becomes rising edge of the clock, with the last bit indicating active again only when temperature falls below TLOW, whether a read or write operation is intended. During and remains active until cleared by a read operation the ninth clock pulse, the slave being addressed of any register or a successful response to the responds to the master by generating an SMBus Alert Response address. Once the ALERT Acknowledge and pulling SDA low. pin is cleared, the above cycle repeats, with the ALERT pin becoming active when the temperature Data transfer is then initiated and sent over eight equals or exceeds THIGH. The ALERT pin can also be clock pulses followed by an Acknowledge Bit. During cleared by resetting the device with the General Call data transfer SDA must remain stable while SCL is Reset command. This action also clears the state of high, because any change in SDA while SCL is high the internal registers in the device, returning the will be interpreted as a START or STOP signal. device to Comparator mode (TM = 0). Once all data have been transferred, the master generates a STOP condition indicated by pulling SDA from low to high, while SCL is high. 9 Submit Documentation Feedback |
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