Datenblatt-Suchmaschine für elektronische Bauteile |
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AD5025BRUZ-REEL7 Datenblatt(PDF) 6 Page - Analog Devices |
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AD5025BRUZ-REEL7 Datenblatt(HTML) 6 Page - Analog Devices |
6 / 33 page AD5025/45/65 Preliminary Technical Data TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and Figure 5. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter Limit at TMIN, TMAX VDD = 2.7 V to 5.5 V Unit Conditions/Comments t11 t2 t3 t4 t5 t6 t7 t8 t8 t9 t10 t11 t12 t13 t14 t15 t162, 3 t173 t183 t193 t20 20 10 10 16.5 5 5 0 1.9 10.5 16.5 0 20 20 10 10 10.6 22 5 8 0 20 ns min ns min ns min ns min ns min ns min ns min us min us min ns min ns min ns min ns min ns min ns min us min ns max ns min ns min ns min ns min SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge set-up time Data set-up time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time (single channel update) Minimum SYNC high time ( all channel update) SYNC rising edge to SCLK fall ignore SCLK falling edge to SYNC fall ignore LDAC pulse width low SCLK falling edge to LDAC rising edge CLR pulse width low SCLK falling edge to LDAC falling edge CLR pulse activation time SCLK rising edge to SDO valid SCLK falling edge to SYNC rising edge SYNC rising edge to SCLK rising edge SYNC rising edge to LDAC falling edge PDL pulse width activation time 1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested. 2 Measured with the load circuit of Figure 16. t16 determines the maximum SCLK frequency in daisy-chain mode. 3 Daisy-chain mode only. 2mA IOL 2mA IOH VOH (MIN) TO OUTPUT PIN CL 50pF Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications Rev. PrB | Page 6 of 3 3 |
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Ähnliche Beschreibung - AD5025BRUZ-REEL7 |
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