Datenblatt-Suchmaschine für elektronische Bauteile |
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TDA9150B Datenblatt(PDF) 7 Page - NXP Semiconductors |
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TDA9150B Datenblatt(HTML) 7 Page - NXP Semiconductors |
7 / 36 page July 1994 7 Philips Semiconductors Preliminary specification Programmable deflection controller TDA9150B Table 2 Control bits. CONTROL BIT LOGIC FUNCTION LFSS 0 Line stop: EW output current becomes zero and the vertical output current is reduced to 20% of the adjusted value. LFSS becomes logic 0 after a HIGH on PON. 1 Line start enabled: the soft start mechanism is now activated. DINT 0 De-interlace on: the VA pulse is sampled at a position selected with control bit DIP. 1 De-interlace off: the VA pulse is sampled with the system clock and the detected rising edge is used as vertical reset. BLDS 0 Aquadag selected. 1 Bleeder selected. GBS 0 Becomes logic 0 after power-on. 1 Guard band 48/12 lines. VAP 0 Positive VA edge detection. 1 Negative VA edge detection. FBL 0 Horizontal flyback slicing level = 3.9 V. 1 Horizontal flyback slicing level = 1.3 V. CSU 0 No clamping suppression, standard mode of operation. 1 Clamping suppression in wait, stop and protection modes (used in systems with e.g. TDA4680/81). PRD 0 No defeat of HOUT, the over voltage information is only written in the PROT status bit. 1 HOUT is defeated and status bit PROT is set when over voltage is detected. DIP 0 VA is sampled 42 clock pulses after the leading edge of HA. 1VA is sampled 258 clock pulses after the leading edge of HA. CPR 0 Nominal amplitude. 1 Compression to 75% of adjusted amplitude, used for display of 16 : 9 standard pictures on 4 : 3 displays. VPR 0 Nominal amplitude (100%) during wait, stop and clipping. 1 Amplitude reduced to 20% during wait, stop and clipping. |
Ähnliche Teilenummer - TDA9150B |
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Ähnliche Beschreibung - TDA9150B |
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