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TSA5518M Datenblatt(PDF) 6 Page - NXP Semiconductors |
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TSA5518M Datenblatt(HTML) 6 Page - NXP Semiconductors |
6 / 20 page 1997 Mar 07 6 Philips Semiconductors Product specification 1.3 GHz bidirectional I2C-bus controlled synthesizer TSA5518M Read mode The read data format is summarised in Table 5. Data can be read out of the device by setting the R/W bit to logic 1. After the slave address has been recognized, the device generates an acknowledge pulse and the status word is transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH of the SCL clock signal. A second data byte can be read out of the device if the processor generates an acknowledge on the SDA line. End of transmission will occur if no acknowledge from the processor occurs.The device will then release the data line to allow the processor to generate a STOP condition. When the port P6 is used as input, it must be programmed in its high-impedance state. The POR flag (Power-on reset) is set to logic 1 when VCC goes below 3 V and at power-on. It is reset when an end of data is detected by the device (end of a READ sequence). Control of the loop is made possible with the in-lock flag FL which indicates (FL = 1) when the loop is phase-locked. A built-in % level A/D converter is available on I/O port P6. This converter can be used to feed AFC information to the controller from the IF section of the television as illustrated in the typical application circuit in Fig.2. The relationship between bit A2, A1 and A0 and the input voltage on port P6 is given in Table 6. Table 5 Read data format Notes 1. See Table 7. 2. POR: Power-on reset flag. (POR = 1 on power-on). 3. FL: in lock flag (FL = 1 when the loop is phase-locked). 4. A2, A1, A0: digital outputs of the 5 level A/D converter (see Table 6). Accuracy is 1 ⁄2 LSB. MSB is transmitted first. 5. Upon an acknowledge pulse from the controller, the device transfers the status byte again. If no acknowledge pulse from the controller is received, data read is terminated. BYTE DESCRIPTION MSB LSB ACKNOWLEDGE 1 address 11000 MA1(1) MA0(1) 1 LOW from device 2, .. status byte(s) POR(2) FL(3) 000 A2(4) A1(4) A0(4) note 5 Table 6 A/D converter levels Accuracy on the switching levels is ±0.02V CC. Table 7 Address selection VOLTAGE APPLIED ON PIN P6 A2 A1 A0 0.6VCC to 5.5 V 1 0 0 0.45VCC to 0.6VCC 01 1 0.3VCC to 0.45VCC 01 0 0.15VCC to 0.3VCC 00 1 0 to 0.15VCC 00 0 VOLTAGE APPLIED ON PIN AS MA1 MA0 0 to 0.1VCC 00 always valid 0 1 0.4 to 0.6VCC 10 0.9VCC to VCC 11 Address selection The module address contains programmable address bits (MA1 and MA0) which offer the possibility of having several synthesizers (up to 3) in one system by applying a specific voltage on AS input. The relationship between MA1 and MA0 and the input voltage on AS input is given in Table 7. Frequency lock flag (FL) definition When the FL flag is logic 1, the maximum frequency deviation dF from stable frequency can be expressed as: with: KVCO = oscillator slope (Hz/V) ICP = charge pump current (A) KO =4 × 106 C1, C2 = loop filter capacitors. df K VCO K O ------------- ± I CP × C1 C2 + C1 C2 × --------------------- × = |
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Ähnliche Beschreibung - TSA5518M |
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