REV. 0

AD7843

–3–

Parameter

Unit

Description

2

10

kHz min

2

MHz max

1.5

µs min

Acquisition Time

10

ns min

CS Falling Edge to First DCLK Rising Edge

60

ns max

CS Falling Edge to BUSY Three-State Disabled

3

60

ns max

CS Falling Edge to DOUT Three-State Disabled

200

ns min

DCLK High Pulsewidth

200

ns min

DCLK Low Pulsewidth

60

ns max

DCLK Falling Edge to BUSY Rising Edge

10

ns min

Data Setup Time Prior to DCLK Rising Edge

10

ns min

Data Valid to DCLK Hold Time

3

200

ns max

Data Access Time after DCLK Falling Edge

0

ns min

CS Rising Edge to DCLK Ignored

200

ns max

CS Rising Edge to BUSY High Impedance

4

200

ns max

CS Rising Edge to DOUT High Impedance

NOTES

°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

time of the part and is independent of the bus loading.

Specifications subject to change without notice.

TO

OUTPUT

PIN

50pF

1.6V

200 A

200 A

Figure 1. Load Circuit for Digital Output Timing Specifications