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AD7843ARU-REEL Datenblatt(PDF) 3 Page - Analog Devices |
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AD7843ARU-REEL Datenblatt(HTML) 3 Page - Analog Devices |
3 / 16 page REV. 0 AD7843 –3– Parameter Limit at TMIN, TMAX Unit Description fDCLK 2 10 kHz min 2 MHz max tACQ 1.5 µs min Acquisition Time t1 10 ns min CS Falling Edge to First DCLK Rising Edge t2 60 ns max CS Falling Edge to BUSY Three-State Disabled t3 3 60 ns max CS Falling Edge to DOUT Three-State Disabled t4 200 ns min DCLK High Pulsewidth t5 200 ns min DCLK Low Pulsewidth t6 60 ns max DCLK Falling Edge to BUSY Rising Edge t7 10 ns min Data Setup Time Prior to DCLK Rising Edge t8 10 ns min Data Valid to DCLK Hold Time t9 3 200 ns max Data Access Time after DCLK Falling Edge t10 0 ns min CS Rising Edge to DCLK Ignored t11 200 ns max CS Rising Edge to BUSY High Impedance t12 4 200 ns max CS Rising Edge to DOUT High Impedance NOTES 1Sample tested at 25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V CC) and timed from a voltage level of 1.6 V. 2Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 2.0 V. 4t 12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number i s then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 12, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. Specifications subject to change without notice. TIMING SPECIFICATIONS1 (T A = TMIN to TMAX, unless otherwise noted; VCC = 2.7 V to 3.6 V, VREF = 2.5 V) TO OUTPUT PIN CL 50pF 1.6V IOL 200 A IOH 200 A Figure 1. Load Circuit for Digital Output Timing Specifications |
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