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CS98ULPA877AHLF-T Datenblatt(PDF) 6 Page - Integrated Device Technology |
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CS98ULPA877AHLF-T Datenblatt(HTML) 6 Page - Integrated Device Technology |
6 / 14 page 6 ICS98ULPA877A Advance Information 1177C—05/23/07 NOTE: The PLL must be able to handle spread spectrum induced skew. NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters. NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal, within the value specificied by the Static Phase Offset ( t ∅), after power-up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK# go to a logic low state, enter the power-down mode and later return to active operation. CK and CK# may be left floating after they have been driven low for one complete clock cycle. Timing Requirements Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Max clock frequency freqop 1.8V+0.1V @ 25°C 95 410 MHz Application Frequency Range freqApp 1.8V+0.1V @ 25°C 160 410 MHz Input clock duty cycle dtin 40 60 % CLK stabilization TSTAB 15 µs |
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