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SI5018-BM Datenblatt(PDF) 6 Page - Silicon Laboratories

Teilenummer SI5018-BM
Bauteilbeschribung  SiPHY??OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC
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Hersteller  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SI5018-BM Datenblatt(HTML) 6 Page - Silicon Laboratories

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Si5018
6
Rev. 1.2
Table 2. DC Characteristics
(VDD =2.5 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Current
IDD
108
122
mA
Power Dissipation
PD
270
320
mW
Common Mode Input Voltage (DIN, REFCLK)*
VICM
varies with VDD
—.80 x VDD
—V
Single Ended Input Voltage (DIN, REFCLK)*
VIS
See Figure 1
200
750
mVPP
Differential Input Voltage Swing (DIN, REFCLK)*
VID
See Figure 1
200
1500
mVPP
Input Impedance (DIN, REFCLK)
RIN
Line-to-Line
84
100
116
Differential Output Voltage Swing (DOUT)
OC48
VOD
100
Ω Load
Line-to-Line
780
990
1260
mVPP
Differential Output Voltage Swing (CLKOUT)
OC48
VOD
100
Ω Load
Line-to-Line
550
900
1260
mVPP
Output Common Mode Voltage
(DOUT,CLKOUT)
VOCM
100
Ω Load
Line-to-Line
—VDD
0.23
—V
Output Impedance (DOUT,CLKOUT)
ROUT
Single-ended
84
100
116
Output Short to GND (DOUT,CLKOUT)
ISC(–)
—2531
mA
Output Short to VDD (DOUT,CLKOUT)
ISC(+)
–17.5
–14.5
mA
Input Voltage Low (LVTTL Inputs)
VIL
——
.8
V
Input Voltage High (LVTTL Inputs)
VIH
2.0
V
Input Low Current (LVTTL Inputs)
IIL
——10
µA
Input High Current (LVTTL Inputs)
IIH
——10
µA
Output Voltage Low (LVTTL Outputs)
VOL
IO =2mA
0.4
V
Output Voltage High (LVTTL Outputs)
VOH
IO =2mA
2.4
V
Input Impedance (LVTTL Inputs)
RIN
10
k
PWRDN/CAL Leakage Current
IPWRDN
VPWRDN ≥ 0.8 V
15
25
35
µA
*Note: The DIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage swing
of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (VID min), and
the unused input must be ac coupled to ground. When driving differentially, the difference between the positive and
negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this range.) In either
case, the voltage applied to any individual pin (DIN+, DIN–, REFCLK+, or REFCLK–) must not exceed the specified
maximum Input Voltage Range (VIS max).


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