Datenblatt-Suchmaschine für elektronische Bauteile |
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SI5325 Datenblatt(PDF) 6 Page - Silicon Laboratories |
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SI5325 Datenblatt(HTML) 6 Page - Silicon Laboratories |
6 / 14 page Si5325 6 Preliminary Rev. 0.26 2. Pin Descriptions: Si5325 Pin numbers are preliminary and subject to change. 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 NC NC RST C2B INT_C1B GND VDD GND CS_CA SCL SDA_SDO A1 A2_SS SDI GND Pad A0 NC 9 18 19 28 NC NC Table 3. Si5325 Pin Descriptions Pin # Pin Name I/O Signal Level Description 1 RST ILVCMOS External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state and forces the device registers to their default value. Clock outputs are tristated during reset. After rising edge of RST signal, the Si5325 will perform an internal self-calibration. This pin has a weak pull-up. 2, 7, 9, 14, 18, 19, 20, 30, 33 NC — — No Connect. This pin must be left unconnected for normal operation. 3 INT_C1B O LVCMOS Interrupt/CKIN1 Invalid Indicator. This pin functions as a device interrupt output or an alarm output for CKIN1. If used as an interrupt output, INT_PIN must be set to 1. The pin functions as a maskable interrupt output with active polarity controlled by the INT_POL register bit. If used as an alarm output, the pin functions as a LOS (and optionally FOS) alarm indicator for CKIN1. Set CK1_BAD_PIN = 1 and INT_PIN =0. 0 = CKIN1 present. 1 = LOS (FOS) on CKIN1. The active polarity is controlled by CK_BAD_POL. If no func- tion is selected, the pin tristates. Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5325 Register Map. |
Ähnliche Teilenummer - SI5325 |
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Ähnliche Beschreibung - SI5325 |
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