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ADS8505IBDWRG4 Datenblatt(PDF) 10 Page - Texas Instruments

Teilenummer ADS8505IBDWRG4
Bauteilbeschribung  16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
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Hersteller  TI [Texas Instruments]
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ADS8505IBDWRG4 Datenblatt(HTML) 10 Page - Texas Instruments

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ADS8505
+5V
+
+
+
+
Convert Pulse
40 ns Min
200
2.2
µF
2.2
µF
0.1
µF
10
µF
33.2 k
B15 (MSB)
B14
B13
B12
B11
B10
B9
B8
B0 (LSB)
B1
B2
B3
B4
B5
B6
B7
READING DATA
PARALLEL OUTPUT (After a Conversion)
PARALLEL OUTPUT (During a Conversion)
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
Figure 21. Basic Operation
The ADS8505 outputs full or byte-reading parallel data in binary 2's complement data output format. The parallel
output is active when R/C (pin 24) is high and CS (pin 25) is low. Any other combination of CS and R/C 3-states
the parallel output. Valid conversion data can be read in a full parallel, 16-bit word or two 8-bit bytes on pins
6-13 and pins 15-22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle. Refer to
Table 2 for ideal output codes and Figure 22 for bit locations relative to the state of BYTE.
Table 2. Ideal Input Voltages and Output Codes
DIGITAL OUTPUT BINARY 2'S COMPLEMENT
DESCRIPTION
ANALOG INPUT
BINARY CODE
HEX CODE
Full-scale range
±10 V
Least significant bit (LSB)
305
µV
Full scale (10 V-1 LSB)
9.999695 V
0111 1111 1111 1111
7FFF
Midscale
0 V
0000 0000 0000 0000
0000
One LSB below midscale
-305
µV
1111 1111 1111 1111
FFFF
–Full scale
-10 V
1000 0000 0000 0000
8000
After conversion n is completed and the output registers have been updated, BUSY (pin 26) goes high. Valid
data from conversion n is available on D15-D0 (pins 6-13 and 15-22). BUSY going high can be used to latch the
data. Refer to Table 3, Figure 23, Figure 24, and Figure 25 for timing specifications.
After conversion n has been initiated, valid data from conversion n-1 can be read and is valid up to t2 (2.2 µs
typ) after the start of conversion n. Do not attempt to read data from t2 (2.2 µs typ) after the start of conversion n
until BUSY (pin 26) goes high; this may result in reading invalid data. Refer to Table 3, Figure 23, Figure 24, and
Figure 25 for timing specifications.
Note: For the best possible performance, data should not be read during a conversion. The switching noise of
the asynchronous data transfer can cause digital feedthrough degrading converter performance.
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