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74LCX374_07 Datenblatt(Datasheet) 2 Page - Fairchild Semiconductor

Teile-Nr. 74LCX374_07
Beschreibung  Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs
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Hersteller  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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74LCX374 Rev. 2.0.0
Logic Symbol
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
Pad Assignments for DQFN
(Top View)
Pin Descriptions
Truth Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
Z
= High Impedance
= LOW-to-HIGH Transition
O0 = Previous O0 before HIGH-to-LOW of CP
Functional Description
The LCX374 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the state
of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) tran-
sition. With the Output Enable (OE) LOW, the contents of
the eight flip-flops are available at the outputs. When the
OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the
flip-flops.
D0 D1 D2 D3 D4 D5 D6 D7
O0
OE
CP
O1 O2 O3 O4 O5 O6 O7
D0
D1
O1
O2
D2
D3
O3
GND
O0
D7
D6
O6
O5
D5
D4
O4
CP
O7
VCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
D0
D1
O1
O2
D2
D3
O3
GND
O0
D7
D6
O6
O5
D5
D4
O4
CP
O7
VCC
120
2
3
4
5
6
7
8
9
10
11
19
18
17
16
15
14
13
12
OE
Pin Names
Description
D0–D7
Data Inputs
CP
Clock Pulse Input
OE
Output Enable Input
O0–O7
3-STATE Outputs
Inputs
Outputs
Dn
CP
OE
On
HL
H
LL
L
XL
L
O0
XX
HZ
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
CP
O0
CP
OE
O1
O2
O3
O4
O5
O6
O7
D0
D1
D2
D3
D4
D5
D6
D7
D
O
CP
D
O
CP
D
O
CP
D
O
CP
D
O
CP
D
O
CP
D
O
CP
D
O




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