Datenblatt-Suchmaschine für elektronische Bauteile |
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SN74ALVC00DGVR Datenblatt(PDF) 1 Page - Texas Instruments |
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SN74ALVC00DGVR Datenblatt(HTML) 1 Page - Texas Instruments |
1 / 16 page www.ti.com FEATURES D, DGV, NS, OR PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1A 1B 1Y 2A 2B 2Y GND VCC 4B 4A 4Y 3B 3A 3Y RGY PACKAGE (TOP VIEW) 1 14 7 8 2 3 4 5 6 13 12 11 10 9 4B 4A 4Y 3B 3A 1B 1Y 2A 2B 2Y DESCRIPTION/ORDERING INFORMATION A B Y SN74ALVC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCES115G – JULY 1997 – REVISED AUGUST 2004 • ESD Protection Exceeds JESD 22 • Operates From 1.65 V to 3.6 V – 2000-V Human-Body Model (A114-A) • Max tpd of 3 ns at 3.3 V – 200-V Machine Model (A115-A) • ±24-mA Output Drive at 3.3 V – 1000-V Charged-Device Model (C101) • Latch-Up Performance Exceeds 250 mA Per JESD 17 This quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVC00 performs the Boolean function Y = A · B or Y = A + B in positive logic. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING QFN - RGY Tape and reel SN74ALVC00RGYR VA00 Tube SN74ALVC00D SOIC - D ALVC00 Tape and reel SN74ALVC00DR -40 °C to 85°C SOP - NS Tape and reel SN74ALVC00NSR ALVC00 TSSOP - PW Tape and reel SN74ALVC00PWR VA00 TVSOP - DGV Tape and reel SN74ALVC00DGVR VA00 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS OUTPUT Y A B H H L L X H X L H LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1997–2004, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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