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74ALVC374PW Datenblatt(PDF) 1 Page - NXP Semiconductors |
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74ALVC374PW Datenblatt(HTML) 1 Page - NXP Semiconductors |
1 / 17 page 1. General description The 74ALVC374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition. When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 74ALVC374 is functionally identical to the 74ALVC574, but has a different pin arrangement. 2. Features s Wide supply voltage range from 1.65 V to 3.6 V s 3.6 V tolerant inputs/outputs s CMOS low power consumption s Direct interface with TTL levels (2.7 V to 3.6 V) s Power-down mode s Latch-up performance exceeds 250 mA s Complies with JEDEC standards: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8B/JESD36 (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A 115-A exceeds 200 V 74ALVC374 Octal D-type flip-flop; positive-edge trigger; 3-state Rev. 02 — 17 October 2007 Product data sheet |
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Ähnliche Beschreibung - 74ALVC374PW |
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